usbrefdesign.tan.qmsg

来自「这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序」· QMSG 代码 · 共 16 行 · 第 1/3 页

{ "Warning" "WTAN_CLOCK_SETTING_NOT_USED" "HalfClock_settings " "Warning: Clock Setting \"HalfClock_settings\" is unassigned" {  } {  } 0 0 "Clock Setting \"%1!s!\" is unassigned" 0 0}
{ "Warning" "WTAN_CLOCK_SETTING_NOT_USED" "QuarterClock_settings " "Warning: Clock Setting \"QuarterClock_settings\" is unassigned" {  } {  } 0 0 "Clock Setting \"%1!s!\" is unassigned" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sclk register TX_state.TX_state1 register LED\[7\]~reg0 207.25 MHz 4.825 ns Internal " "Info: Clock \"sclk\" has Internal fmax of 207.25 MHz between source register \"TX_state.TX_state1\" and destination register \"LED\[7\]~reg0\" (period= 4.825 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.116 ns + Longest register register " "Info: + Longest register to register delay is 4.116 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TX_state.TX_state1 1 REG LC_X8_Y10_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N8; Fanout = 3; REG Node = 'TX_state.TX_state1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { TX_state.TX_state1 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.894 ns) + CELL(0.200 ns) 1.094 ns LED\[0\]~279 2 COMB LC_X8_Y10_N7 8 " "Info: 2: + IC(0.894 ns) + CELL(0.200 ns) = 1.094 ns; Loc. = LC_X8_Y10_N7; Fanout = 8; COMB Node = 'LED\[0\]~279'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.094 ns" { TX_state.TX_state1 LED[0]~279 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.779 ns) + CELL(1.243 ns) 4.116 ns LED\[7\]~reg0 3 REG LC_X6_Y10_N8 1 " "Info: 3: + IC(1.779 ns) + CELL(1.243 ns) = 4.116 ns; Loc. = LC_X6_Y10_N8; Fanout = 1; REG Node = 'LED\[7\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.022 ns" { LED[0]~279 LED[7]~reg0 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.443 ns ( 35.06 % ) " "Info: Total cell delay = 1.443 ns ( 35.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.673 ns ( 64.94 % ) " "Info: Total interconnect delay = 2.673 ns ( 64.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.116 ns" { TX_state.TX_state1 LED[0]~279 LED[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.116 ns" { TX_state.TX_state1 LED[0]~279 LED[7]~reg0 } { 0.000ns 0.894ns 1.779ns } { 0.000ns 0.200ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"sclk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns sclk 1 CLK PIN_18 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 13; CLK Node = 'sclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns LED\[7\]~reg0 2 REG LC_X6_Y10_N8 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X6_Y10_N8; Fanout = 1; REG Node = 'LED\[7\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { sclk LED[7]~reg0 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk LED[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout LED[7]~reg0 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"sclk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns sclk 1 CLK PIN_18 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 13; CLK Node = 'sclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns TX_state.TX_state1 2 REG LC_X8_Y10_N8 3 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X8_Y10_N8; Fanout = 3; REG Node = 'TX_state.TX_state1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { sclk TX_state.TX_state1 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk TX_state.TX_state1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout TX_state.TX_state1 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk LED[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout LED[7]~reg0 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk TX_state.TX_state1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout TX_state.TX_state1 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.116 ns" { TX_state.TX_state1 LED[0]~279 LED[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.116 ns" { TX_state.TX_state1 LED[0]~279 LED[7]~reg0 } { 0.000ns 0.894ns 1.779ns } { 0.000ns 0.200ns 1.243ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk LED[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout LED[7]~reg0 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk TX_state.TX_state1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout TX_state.TX_state1 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "LED\[7\]~reg0 USB_RXE sclk 5.685 ns register " "Info: tsu for register \"LED\[7\]~reg0\" (data pin = \"USB_RXE\", clock pin = \"sclk\") is 5.685 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.171 ns + Longest pin register " "Info: + Longest pin to register delay is 9.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns USB_RXE 1 PIN PIN_1 6 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_1; Fanout = 6; PIN Node = 'USB_RXE'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { USB_RXE } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.277 ns) + CELL(0.740 ns) 6.149 ns LED\[0\]~279 2 COMB LC_X8_Y10_N7 8 " "Info: 2: + IC(4.277 ns) + CELL(0.740 ns) = 6.149 ns; Loc. = LC_X8_Y10_N7; Fanout = 8; COMB Node = 'LED\[0\]~279'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.017 ns" { USB_RXE LED[0]~279 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.779 ns) + CELL(1.243 ns) 9.171 ns LED\[7\]~reg0 3 REG LC_X6_Y10_N8 1 " "Info: 3: + IC(1.779 ns) + CELL(1.243 ns) = 9.171 ns; Loc. = LC_X6_Y10_N8; Fanout = 1; REG Node = 'LED\[7\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.022 ns" { LED[0]~279 LED[7]~reg0 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 33.97 % ) " "Info: Total cell delay = 3.115 ns ( 33.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.056 ns ( 66.03 % ) " "Info: Total interconnect delay = 6.056 ns ( 66.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.171 ns" { USB_RXE LED[0]~279 LED[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.171 ns" { USB_RXE USB_RXE~combout LED[0]~279 LED[7]~reg0 } { 0.000ns 0.000ns 4.277ns 1.779ns } { 0.000ns 1.132ns 0.740ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"sclk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns sclk 1 CLK PIN_18 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 13; CLK Node = 'sclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns LED\[7\]~reg0 2 REG LC_X6_Y10_N8 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X6_Y10_N8; Fanout = 1; REG Node = 'LED\[7\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { sclk LED[7]~reg0 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk LED[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout LED[7]~reg0 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.171 ns" { USB_RXE LED[0]~279 LED[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.171 ns" { USB_RXE USB_RXE~combout LED[0]~279 LED[7]~reg0 } { 0.000ns 0.000ns 4.277ns 1.779ns } { 0.000ns 1.132ns 0.740ns 1.243ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk LED[7]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout LED[7]~reg0 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sclk LED\[3\] LED\[3\]~reg0 9.032 ns register " "Info: tco from clock \"sclk\" to destination pin \"LED\[3\]\" through register \"LED\[3\]~reg0\" is 9.032 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 3.819 ns + Longest register " "Info: + Longest clock path from clock \"sclk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns sclk 1 CLK PIN_18 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 13; CLK Node = 'sclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns LED\[3\]~reg0 2 REG LC_X8_Y10_N9 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X8_Y10_N9; Fanout = 1; REG Node = 'LED\[3\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { sclk LED[3]~reg0 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk LED[3]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout LED[3]~reg0 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.837 ns + Longest register pin " "Info: + Longest register to pin delay is 4.837 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LED\[3\]~reg0 1 REG LC_X8_Y10_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N9; Fanout = 1; REG Node = 'LED\[3\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { LED[3]~reg0 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.515 ns) + CELL(2.322 ns) 4.837 ns LED\[3\] 2 PIN PIN_125 0 " "Info: 2: + IC(2.515 ns) + CELL(2.322 ns) = 4.837 ns; Loc. = PIN_125; Fanout = 0; PIN Node = 'LED\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.837 ns" { LED[3]~reg0 LED[3] } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 48.00 % ) " "Info: Total cell delay = 2.322 ns ( 48.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.515 ns ( 52.00 % ) " "Info: Total interconnect delay = 2.515 ns ( 52.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.837 ns" { LED[3]~reg0 LED[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.837 ns" { LED[3]~reg0 LED[3] } { 0.000ns 2.515ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk LED[3]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout LED[3]~reg0 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.837 ns" { LED[3]~reg0 LED[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.837 ns" { LED[3]~reg0 LED[3] } { 0.000ns 2.515ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "LED\[1\]~reg0 USB_DATA\[1\] sclk -1.108 ns register " "Info: th for register \"LED\[1\]~reg0\" (data pin = \"USB_DATA\[1\]\", clock pin = \"sclk\") is -1.108 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 3.819 ns + Longest register " "Info: + Longest clock path from clock \"sclk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns sclk 1 CLK PIN_18 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 13; CLK Node = 'sclk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns LED\[1\]~reg0 2 REG LC_X8_Y10_N0 1 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X8_Y10_N0; Fanout = 1; REG Node = 'LED\[1\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { sclk LED[1]~reg0 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk LED[1]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout LED[1]~reg0 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.148 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns USB_DATA\[1\] 1 PIN PIN_133 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_133; Fanout = 1; PIN Node = 'USB_DATA\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { USB_DATA[1] } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.736 ns) + CELL(0.280 ns) 5.148 ns LED\[1\]~reg0 2 REG LC_X8_Y10_N0 1 " "Info: 2: + IC(3.736 ns) + CELL(0.280 ns) = 5.148 ns; Loc. = LC_X8_Y10_N0; Fanout = 1; REG Node = 'LED\[1\]~reg0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.016 ns" { USB_DATA[1] LED[1]~reg0 } "NODE_NAME" } } { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 27.43 % ) " "Info: Total cell delay = 1.412 ns ( 27.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.736 ns ( 72.57 % ) " "Info: Total interconnect delay = 3.736 ns ( 72.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.148 ns" { USB_DATA[1] LED[1]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.148 ns" { USB_DATA[1] USB_DATA[1]~combout LED[1]~reg0 } { 0.000ns 0.000ns 3.736ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { sclk LED[1]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { sclk sclk~combout LED[1]~reg0 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.148 ns" { USB_DATA[1] LED[1]~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.148 ns" { USB_DATA[1] USB_DATA[1]~combout LED[1]~reg0 } { 0.000ns 0.000ns 3.736ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}