📄 usbrefdesign.tan.rpt
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; N/A ; None ; 8.372 ns ; LED[2]~reg0 ; LED[2] ; sclk ;
; N/A ; None ; 7.285 ns ; LED[6]~reg0 ; LED[6] ; sclk ;
; N/A ; None ; 7.285 ns ; LED[5]~reg0 ; LED[5] ; sclk ;
+-------+--------------+------------+-------------+--------+------------+
+---------------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+-------------+--------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+-------------+--------------------+----------+
; N/A ; None ; -1.108 ns ; USB_DATA[1] ; LED[1]~reg0 ; sclk ;
; N/A ; None ; -1.147 ns ; USB_DATA[0] ; LED[0]~reg0 ; sclk ;
; N/A ; None ; -1.382 ns ; USB_DATA[2] ; LED[2]~reg0 ; sclk ;
; N/A ; None ; -1.620 ns ; USB_DATA[6] ; LED[6]~reg0 ; sclk ;
; N/A ; None ; -1.707 ns ; USB_DATA[4] ; LED[4]~reg0 ; sclk ;
; N/A ; None ; -1.864 ns ; USB_DATA[7] ; LED[7]~reg0 ; sclk ;
; N/A ; None ; -1.899 ns ; USB_DATA[5] ; LED[5]~reg0 ; sclk ;
; N/A ; None ; -1.959 ns ; USB_RXE ; TX_state.TX_state1 ; sclk ;
; N/A ; None ; -1.963 ns ; USB_DATA[3] ; LED[3]~reg0 ; sclk ;
; N/A ; None ; -1.963 ns ; USB_RXE ; TX_state.TX_state0 ; sclk ;
; N/A ; None ; -2.166 ns ; USB_RXE ; TX_state.TX_state3 ; sclk ;
; N/A ; None ; -2.167 ns ; USB_RXE ; USB_RD~reg0 ; sclk ;
; N/A ; None ; -2.430 ns ; USB_RXE ; TX_state.TX_state2 ; sclk ;
; N/A ; None ; -4.015 ns ; USB_RXE ; LED[0]~reg0 ; sclk ;
; N/A ; None ; -4.015 ns ; USB_RXE ; LED[1]~reg0 ; sclk ;
; N/A ; None ; -4.015 ns ; USB_RXE ; LED[2]~reg0 ; sclk ;
; N/A ; None ; -4.015 ns ; USB_RXE ; LED[3]~reg0 ; sclk ;
; N/A ; None ; -4.015 ns ; USB_RXE ; LED[4]~reg0 ; sclk ;
; N/A ; None ; -4.015 ns ; USB_RXE ; LED[5]~reg0 ; sclk ;
; N/A ; None ; -4.015 ns ; USB_RXE ; LED[6]~reg0 ; sclk ;
; N/A ; None ; -5.131 ns ; USB_RXE ; LED[7]~reg0 ; sclk ;
+---------------+-------------+-----------+-------------+--------------------+----------+
+---------------------------------------------------------------------------------------+
; Minimum tco ;
+---------------+------------------+----------------+-------------+--------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+-------------+--------+------------+
; N/A ; None ; 7.285 ns ; LED[5]~reg0 ; LED[5] ; sclk ;
; N/A ; None ; 7.285 ns ; LED[6]~reg0 ; LED[6] ; sclk ;
; N/A ; None ; 8.372 ns ; LED[2]~reg0 ; LED[2] ; sclk ;
; N/A ; None ; 8.485 ns ; LED[1]~reg0 ; LED[1] ; sclk ;
; N/A ; None ; 8.511 ns ; LED[4]~reg0 ; LED[4] ; sclk ;
; N/A ; None ; 8.885 ns ; LED[7]~reg0 ; LED[7] ; sclk ;
; N/A ; None ; 8.905 ns ; LED[0]~reg0 ; LED[0] ; sclk ;
; N/A ; None ; 8.969 ns ; USB_RD~reg0 ; USB_RD ; sclk ;
; N/A ; None ; 9.032 ns ; LED[3]~reg0 ; LED[3] ; sclk ;
+---------------+------------------+----------------+-------------+--------+------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Ignored Timing Assignments ;
+----------------+-----------------------+------+--------------------------------+-------------+--------------------------------------------------------------------------+
; Option ; Setting ; From ; To ; Entity Name ; Help ;
+----------------+-----------------------+------+--------------------------------+-------------+--------------------------------------------------------------------------+
; Clock Settings ; HalfClock_settings ; ; DivideClock:inst5|HalfClock ; ; No element named DivideClock:inst5|HalfClock was found in the netlist ;
; Clock Settings ; QuarterClock_settings ; ; DivideClock:inst5|QuarterClock ; ; No element named DivideClock:inst5|QuarterClock was found in the netlist ;
+----------------+-----------------------+------+--------------------------------+-------------+--------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Mon Jun 09 13:17:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off USBRefDesign -c USBRefDesign
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "sclk" is an undefined clock
Warning: Clock Setting "HalfClock_settings" is unassigned
Warning: Clock Setting "QuarterClock_settings" is unassigned
Info: Clock "sclk" has Internal fmax of 207.25 MHz between source register "TX_state.TX_state1" and destination register "LED[7]~reg0" (period= 4.825 ns)
Info: + Longest register to register delay is 4.116 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N8; Fanout = 3; REG Node = 'TX_state.TX_state1'
Info: 2: + IC(0.894 ns) + CELL(0.200 ns) = 1.094 ns; Loc. = LC_X8_Y10_N7; Fanout = 8; COMB Node = 'LED[0]~279'
Info: 3: + IC(1.779 ns) + CELL(1.243 ns) = 4.116 ns; Loc. = LC_X6_Y10_N8; Fanout = 1; REG Node = 'LED[7]~reg0'
Info: Total cell delay = 1.443 ns ( 35.06 % )
Info: Total interconnect delay = 2.673 ns ( 64.94 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "sclk" to destination register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 13; CLK Node = 'sclk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X6_Y10_N8; Fanout = 1; REG Node = 'LED[7]~reg0'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: - Longest clock path from clock "sclk" to source register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 13; CLK Node = 'sclk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X8_Y10_N8; Fanout = 3; REG Node = 'TX_state.TX_state1'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "LED[7]~reg0" (data pin = "USB_RXE", clock pin = "sclk") is 5.685 ns
Info: + Longest pin to register delay is 9.171 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_1; Fanout = 6; PIN Node = 'USB_RXE'
Info: 2: + IC(4.277 ns) + CELL(0.740 ns) = 6.149 ns; Loc. = LC_X8_Y10_N7; Fanout = 8; COMB Node = 'LED[0]~279'
Info: 3: + IC(1.779 ns) + CELL(1.243 ns) = 9.171 ns; Loc. = LC_X6_Y10_N8; Fanout = 1; REG Node = 'LED[7]~reg0'
Info: Total cell delay = 3.115 ns ( 33.97 % )
Info: Total interconnect delay = 6.056 ns ( 66.03 % )
Info: + Micro setup delay of destination is 0.333 ns
Info: - Shortest clock path from clock "sclk" to destination register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 13; CLK Node = 'sclk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X6_Y10_N8; Fanout = 1; REG Node = 'LED[7]~reg0'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: tco from clock "sclk" to destination pin "LED[3]" through register "LED[3]~reg0" is 9.032 ns
Info: + Longest clock path from clock "sclk" to source register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 13; CLK Node = 'sclk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X8_Y10_N9; Fanout = 1; REG Node = 'LED[3]~reg0'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Longest register to pin delay is 4.837 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N9; Fanout = 1; REG Node = 'LED[3]~reg0'
Info: 2: + IC(2.515 ns) + CELL(2.322 ns) = 4.837 ns; Loc. = PIN_125; Fanout = 0; PIN Node = 'LED[3]'
Info: Total cell delay = 2.322 ns ( 48.00 % )
Info: Total interconnect delay = 2.515 ns ( 52.00 % )
Info: th for register "LED[1]~reg0" (data pin = "USB_DATA[1]", clock pin = "sclk") is -1.108 ns
Info: + Longest clock path from clock "sclk" to destination register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 13; CLK Node = 'sclk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X8_Y10_N0; Fanout = 1; REG Node = 'LED[1]~reg0'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: + Micro hold delay of destination is 0.221 ns
Info: - Shortest pin to register delay is 5.148 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_133; Fanout = 1; PIN Node = 'USB_DATA[1]'
Info: 2: + IC(3.736 ns) + CELL(0.280 ns) = 5.148 ns; Loc. = LC_X8_Y10_N0; Fanout = 1; REG Node = 'LED[1]~reg0'
Info: Total cell delay = 1.412 ns ( 27.43 % )
Info: Total interconnect delay = 3.736 ns ( 72.57 % )
Info: Minimum tco from clock "sclk" to destination pin "LED[5]" through register "LED[5]~reg0" is 7.285 ns
Info: + Shortest clock path from clock "sclk" to source register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 13; CLK Node = 'sclk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X8_Y10_N3; Fanout = 1; REG Node = 'LED[5]~reg0'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Shortest register to pin delay is 3.090 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N3; Fanout = 1; REG Node = 'LED[5]~reg0'
Info: 2: + IC(0.768 ns) + CELL(2.322 ns) = 3.090 ns; Loc. = PIN_129; Fanout = 0; PIN Node = 'LED[5]'
Info: Total cell delay = 2.322 ns ( 75.15 % )
Info: Total interconnect delay = 0.768 ns ( 24.85 % )
Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
Info: Allocated 100 megabytes of memory during processing
Info: Processing ended: Mon Jun 09 13:17:32 2008
Info: Elapsed time: 00:00:01
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