📄 usbrefdesign.tan.rpt
字号:
Classic Timing Analyzer report for USBRefDesign
Mon Jun 09 13:17:32 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'sclk'
6. tsu
7. tco
8. th
9. Minimum tco
10. Ignored Timing Assignments
11. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+--------------------+-------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------------------+-------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 5.685 ns ; USB_RXE ; LED[7]~reg0 ; -- ; sclk ; 0 ;
; Worst-case tco ; N/A ; None ; 9.032 ns ; LED[3]~reg0 ; LED[3] ; sclk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -1.108 ns ; USB_DATA[1] ; LED[1]~reg0 ; -- ; sclk ; 0 ;
; Worst-case Minimum tco ; N/A ; None ; 7.285 ns ; LED[5]~reg0 ; LED[5] ; sclk ; -- ; 0 ;
; Clock Setup: 'sclk' ; N/A ; None ; 207.25 MHz ( period = 4.825 ns ) ; TX_state.TX_state1 ; LED[7]~reg0 ; sclk ; sclk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+--------------------+-------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM1270T144C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; On ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; sclk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'sclk' ;
+-------+------------------------------------------------+--------------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 207.25 MHz ( period = 4.825 ns ) ; TX_state.TX_state1 ; LED[7]~reg0 ; sclk ; sclk ; None ; None ; 4.116 ns ;
; N/A ; 252.02 MHz ( period = 3.968 ns ) ; TX_state.TX_state1 ; USB_RD~reg0 ; sclk ; sclk ; None ; None ; 3.259 ns ;
; N/A ; 252.65 MHz ( period = 3.958 ns ) ; TX_state.TX_state3 ; USB_RD~reg0 ; sclk ; sclk ; None ; None ; 3.249 ns ;
; N/A ; 269.61 MHz ( period = 3.709 ns ) ; TX_state.TX_state1 ; LED[0]~reg0 ; sclk ; sclk ; None ; None ; 3.000 ns ;
; N/A ; 269.61 MHz ( period = 3.709 ns ) ; TX_state.TX_state1 ; LED[1]~reg0 ; sclk ; sclk ; None ; None ; 3.000 ns ;
; N/A ; 269.61 MHz ( period = 3.709 ns ) ; TX_state.TX_state1 ; LED[2]~reg0 ; sclk ; sclk ; None ; None ; 3.000 ns ;
; N/A ; 269.61 MHz ( period = 3.709 ns ) ; TX_state.TX_state1 ; LED[3]~reg0 ; sclk ; sclk ; None ; None ; 3.000 ns ;
; N/A ; 269.61 MHz ( period = 3.709 ns ) ; TX_state.TX_state1 ; LED[4]~reg0 ; sclk ; sclk ; None ; None ; 3.000 ns ;
; N/A ; 269.61 MHz ( period = 3.709 ns ) ; TX_state.TX_state1 ; LED[5]~reg0 ; sclk ; sclk ; None ; None ; 3.000 ns ;
; N/A ; 269.61 MHz ( period = 3.709 ns ) ; TX_state.TX_state1 ; LED[6]~reg0 ; sclk ; sclk ; None ; None ; 3.000 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; USB_RD~reg0 ; USB_RD~reg0 ; sclk ; sclk ; None ; None ; 2.465 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; TX_state.TX_state3 ; TX_state.TX_state3 ; sclk ; sclk ; None ; None ; 2.075 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; TX_state.TX_state2 ; USB_RD~reg0 ; sclk ; sclk ; None ; None ; 1.917 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; TX_state.TX_state2 ; TX_state.TX_state3 ; sclk ; sclk ; None ; None ; 1.912 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; TX_state.TX_state0 ; TX_state.TX_state1 ; sclk ; sclk ; None ; None ; 1.746 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; TX_state.TX_state1 ; TX_state.TX_state2 ; sclk ; sclk ; None ; None ; 1.485 ns ;
+-------+------------------------------------------------+--------------------+--------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+-------------+--------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+-------------+--------------------+----------+
; N/A ; None ; 5.685 ns ; USB_RXE ; LED[7]~reg0 ; sclk ;
; N/A ; None ; 4.569 ns ; USB_RXE ; LED[0]~reg0 ; sclk ;
; N/A ; None ; 4.569 ns ; USB_RXE ; LED[1]~reg0 ; sclk ;
; N/A ; None ; 4.569 ns ; USB_RXE ; LED[2]~reg0 ; sclk ;
; N/A ; None ; 4.569 ns ; USB_RXE ; LED[3]~reg0 ; sclk ;
; N/A ; None ; 4.569 ns ; USB_RXE ; LED[4]~reg0 ; sclk ;
; N/A ; None ; 4.569 ns ; USB_RXE ; LED[5]~reg0 ; sclk ;
; N/A ; None ; 4.569 ns ; USB_RXE ; LED[6]~reg0 ; sclk ;
; N/A ; None ; 2.984 ns ; USB_RXE ; TX_state.TX_state2 ; sclk ;
; N/A ; None ; 2.721 ns ; USB_RXE ; USB_RD~reg0 ; sclk ;
; N/A ; None ; 2.720 ns ; USB_RXE ; TX_state.TX_state3 ; sclk ;
; N/A ; None ; 2.517 ns ; USB_DATA[3] ; LED[3]~reg0 ; sclk ;
; N/A ; None ; 2.517 ns ; USB_RXE ; TX_state.TX_state0 ; sclk ;
; N/A ; None ; 2.513 ns ; USB_RXE ; TX_state.TX_state1 ; sclk ;
; N/A ; None ; 2.453 ns ; USB_DATA[5] ; LED[5]~reg0 ; sclk ;
; N/A ; None ; 2.418 ns ; USB_DATA[7] ; LED[7]~reg0 ; sclk ;
; N/A ; None ; 2.261 ns ; USB_DATA[4] ; LED[4]~reg0 ; sclk ;
; N/A ; None ; 2.174 ns ; USB_DATA[6] ; LED[6]~reg0 ; sclk ;
; N/A ; None ; 1.936 ns ; USB_DATA[2] ; LED[2]~reg0 ; sclk ;
; N/A ; None ; 1.701 ns ; USB_DATA[0] ; LED[0]~reg0 ; sclk ;
; N/A ; None ; 1.662 ns ; USB_DATA[1] ; LED[1]~reg0 ; sclk ;
+-------+--------------+------------+-------------+--------------------+----------+
+-----------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A ; None ; 9.032 ns ; LED[3]~reg0 ; LED[3] ; sclk ;
; N/A ; None ; 8.969 ns ; USB_RD~reg0 ; USB_RD ; sclk ;
; N/A ; None ; 8.905 ns ; LED[0]~reg0 ; LED[0] ; sclk ;
; N/A ; None ; 8.885 ns ; LED[7]~reg0 ; LED[7] ; sclk ;
; N/A ; None ; 8.511 ns ; LED[4]~reg0 ; LED[4] ; sclk ;
; N/A ; None ; 8.485 ns ; LED[1]~reg0 ; LED[1] ; sclk ;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -