usbrefdesign.fit.eqn

这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序

--N1_SRAMce_n is SRAMInterface:inst36|SRAMce_n at LC_X6_Y7_N4
--operation mode is normal

N1_SRAMce_n_lut_out = N1L47 & !N1L54Q & (N1_SRAMce_n # !N1L27);
N1_SRAMce_n = DFFEA(N1_SRAMce_n_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_SRAMoe_n is SRAMInterface:inst36|SRAMoe_n at LC_X7_Y6_N9
--operation mode is normal

N1_SRAMoe_n_lut_out = N1_SRAMoe_n & (N1L57 # N1L971) # !N1L47;
N1_SRAMoe_n = DFFEA(N1_SRAMoe_n_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_SRAMwe_n is SRAMInterface:inst36|SRAMwe_n at LC_X6_Y6_N2
--operation mode is normal

N1_SRAMwe_n_lut_out = !N1L54Q & !N1L16 & (N1_SRAMwe_n # !N1L77);
N1_SRAMwe_n = DFFEA(N1_SRAMwe_n_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--G1_FlashLED is LEDFlasher:inst8|FlashLED at LC_X10_Y4_N3
--operation mode is normal

G1_FlashLED_lut_out = inst62 & (G1_FlashLED $ (!G1L8 & !G1L7));
G1_FlashLED = DFFEA(G1_FlashLED_lut_out, GLOBAL(D1_QuarterClock), VCC, , , , );


--inst26 is inst26 at LC_X10_Y4_N0
--operation mode is normal

B1_LEDs[1]_qfbk = B1_LEDs[1];
inst26 = B1_LEDs[1]_qfbk # G1_FlashLED;

--B1_LEDs[1] is TheDirector:inst|LEDs[1] at LC_X10_Y4_N0
--operation mode is normal

B1_LEDs[1]_sload_eqn = T1L6;
B1_LEDs[1] = DFFEA(B1_LEDs[1]_sload_eqn, GLOBAL(D1_QuarterClock), VCC, , B1L71, , );


--B1_LEDs[0] is TheDirector:inst|LEDs[0] at LC_X10_Y7_N6
--operation mode is normal

B1_LEDs[0]_lut_out = B1L83 & (B1_NextState[3] $ B1_NextState[2]);
B1_LEDs[0] = DFFEA(B1_LEDs[0]_lut_out, GLOBAL(D1_QuarterClock), VCC, , B1L52, , );


--inst42 is inst42 at LC_X10_Y4_N8
--operation mode is normal

inst42 = B1_LEDs[0] # G1_FlashLED;


--inst22 is inst22 at LC_X10_Y4_N1
--operation mode is normal

B1_LEDs[2]_qfbk = B1_LEDs[2];
inst22 = B1_LEDs[2]_qfbk # G1_FlashLED;

--B1_LEDs[2] is TheDirector:inst|LEDs[2] at LC_X10_Y4_N1
--operation mode is normal

B1_LEDs[2]_sload_eqn = T1L7;
B1_LEDs[2] = DFFEA(B1_LEDs[2]_sload_eqn, GLOBAL(D1_QuarterClock), VCC, , B1L71, , );


--inst46 is inst46 at LC_X10_Y4_N4
--operation mode is normal

B1_LEDs[3]_qfbk = B1_LEDs[3];
inst46 = B1_LEDs[3]_qfbk # G1_FlashLED;

--B1_LEDs[3] is TheDirector:inst|LEDs[3] at LC_X10_Y4_N4
--operation mode is normal

B1_LEDs[3]_sload_eqn = T1L8;
B1_LEDs[3] = DFFEA(B1_LEDs[3]_sload_eqn, GLOBAL(D1_QuarterClock), VCC, , B1L71, , );


--H1_lcd_rw is lcd_controller:inst9|lcd_rw at LC_X4_Y8_N1
--operation mode is normal

H1_lcd_rw_lut_out = H1_lcd_rw & (H1L59 # H1L514 # H1L49);
H1_lcd_rw = DFFEA(H1_lcd_rw_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--H1_lcd_rs is lcd_controller:inst9|lcd_rs at LC_X5_Y8_N5
--operation mode is normal

H1_lcd_rs_lut_out = H1_lcd_rs & (H1L79 # H1L69 & M1_LCDrs) # !H1_lcd_rs & H1L69 & M1_LCDrs;
H1_lcd_rs = DFFEA(H1_lcd_rs_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--H1_lcd_enable is lcd_controller:inst9|lcd_enable at LC_X3_Y9_N9
--operation mode is normal

H1_lcd_enable_lut_out = H1L901 # H1L801 # H1_lcd_enable & H1L211;
H1_lcd_enable = DFFEA(H1_lcd_enable_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--E1_CS_n is TempInterface:inst6|CS_n at LC_X14_Y6_N5
--operation mode is normal

E1_CS_n_lut_out = E1L14Q & E1_CS_n & E1L85 # !E1L14Q & (E1L941 # E1_CS_n & E1L85);
E1_CS_n = DFFEA(E1_CS_n_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--E1_SCK is TempInterface:inst6|SCK at LC_X14_Y6_N0
--operation mode is normal

E1_SCK_lut_out = E1L06 # E1L16 # !E1L14Q & E1L941;
E1_SCK = DFFEA(E1_SCK_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--G1_ErrorUSB_read is LEDFlasher:inst8|ErrorUSB_read at LC_X6_Y10_N5
--operation mode is normal

G1_ErrorUSB_read_lut_out = !USB_RXFn_D5 & (Q1_Error # B1_Error);
G1_ErrorUSB_read = DFFEA(G1_ErrorUSB_read_lut_out, GLOBAL(Clock_H5), VCC, , , , );


--M1_USBReadFifo is LCDInterface:inst33|USBReadFifo at LC_X9_Y10_N9
--operation mode is normal

M1_USBReadFifo_lut_out = !M1_NextState[2] & !M1_NextState[0] & !M1_NextState[3] & M1L74;
M1_USBReadFifo = DFFEA(M1_USBReadFifo_lut_out, GLOBAL(D1_HalfClock), VCC, , M1L83, , );


--B1_USBReadFifo is TheDirector:inst|USBReadFifo at LC_X10_Y8_N8
--operation mode is normal

B1_USBReadFifo_lut_out = B1L23 & (B1_USBReadFifo # !B1L93);
B1_USBReadFifo = DFFEA(B1_USBReadFifo_lut_out, GLOBAL(D1_QuarterClock), VCC, , B1L62, , );


--N1_USBReadFifo is SRAMInterface:inst36|USBReadFifo at LC_X6_Y7_N7
--operation mode is normal

N1_USBReadFifo_lut_out = N1_USBReadFifo & (N1L96 # N1L071 & N1L05Q) # !N1_USBReadFifo & N1L071 & N1L05Q;
N1_USBReadFifo = DFFEA(N1_USBReadFifo_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--A1L2 is inst2~17 at LC_X6_Y10_N1
--operation mode is normal

A1L2 = G1_ErrorUSB_read # B1_USBReadFifo # M1_USBReadFifo # N1_USBReadFifo;


--Q1_USBWriteFifo is PassivesInterface:inst61|USBWriteFifo at LC_X13_Y7_N8
--operation mode is normal

Q1_USBWriteFifo_lut_out = Q1L67 & (Q1L77 # Q1_USBWriteFifo & Q1L87);
Q1_USBWriteFifo = DFFEA(Q1_USBWriteFifo_lut_out, GLOBAL(D1_HalfClock), VCC, , Q1L67, , );


--L1_USBWriteFifo is UFMInterface:inst28|USBWriteFifo at LC_X16_Y5_N2
--operation mode is normal

L1_USBWriteFifo_lut_out = L1L53 # L1_USBWriteFifo & !L1L93;
L1_USBWriteFifo = DFFEA(L1_USBWriteFifo_lut_out, GLOBAL(D1_QuarterClock), VCC, , , , );


--N1_USBWriteFifo is SRAMInterface:inst36|USBWriteFifo at LC_X13_Y7_N5
--operation mode is normal

N1_USBWriteFifo_lut_out = N1L37 # N1_USBWriteFifo & (!N1L18 # !N1L181);
N1_USBWriteFifo = DFFEA(N1_USBWriteFifo_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--A1L6 is inst35~13 at LC_X13_Y7_N2
--operation mode is normal

A1L6 = N1_USBWriteFifo # L1_USBWriteFifo # Q1_USBWriteFifo;


--H1_lcd_db[7] is lcd_controller:inst9|lcd_db[7] at LC_X5_Y10_N3
--operation mode is normal

H1_lcd_db[7]_lut_out = H1L411 # H1_lcd_db[7] & H1L283Q & H1L263;
H1_lcd_db[7] = DFFEA(H1_lcd_db[7]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--H1_lcd_db[6] is lcd_controller:inst9|lcd_db[6] at LC_X5_Y9_N9
--operation mode is normal

H1_lcd_db[6]_lut_out = H1L611 # H1L263 & H1_lcd_db[6] & H1L283Q;
H1_lcd_db[6] = DFFEA(H1_lcd_db[6]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--H1_lcd_db[5] is lcd_controller:inst9|lcd_db[5] at LC_X4_Y7_N2
--operation mode is normal

H1_lcd_db[5]_lut_out = H1L09 # H1L911 # H1L021 & H1_lcd_db[5];
H1_lcd_db[5] = DFFEA(H1_lcd_db[5]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--H1_lcd_db[4] is lcd_controller:inst9|lcd_db[4] at LC_X4_Y7_N6
--operation mode is normal

H1_lcd_db[4]_lut_out = H1L221 # H1L09 # H1L021 & H1_lcd_db[4];
H1_lcd_db[4] = DFFEA(H1_lcd_db[4]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--H1_lcd_db[3] is lcd_controller:inst9|lcd_db[3] at LC_X3_Y10_N6
--operation mode is normal

H1_lcd_db[3]_lut_out = H1L621 # H1L421 # H1_lcd_db[3] & H1L021;
H1_lcd_db[3] = DFFEA(H1_lcd_db[3]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--H1_lcd_db[2] is lcd_controller:inst9|lcd_db[2] at LC_X4_Y10_N4
--operation mode is normal

H1_lcd_db[2]_lut_out = H1L031 # H1L821 # H1_lcd_db[2] & H1L021;
H1_lcd_db[2] = DFFEA(H1_lcd_db[2]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--H1_lcd_db[1] is lcd_controller:inst9|lcd_db[1] at LC_X4_Y10_N0
--operation mode is normal

H1_lcd_db[1]_lut_out = H1L231 # H1L821 # H1L021 & H1_lcd_db[1];
H1_lcd_db[1] = DFFEA(H1_lcd_db[1]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--H1_lcd_db[0] is lcd_controller:inst9|lcd_db[0] at LC_X4_Y10_N6
--operation mode is normal

H1_lcd_db[0]_lut_out = H1L531 # H1L331 # H1_lcd_db[0] & H1L021;
H1_lcd_db[0] = DFFEA(H1_lcd_db[0]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[16] is SRAMInterface:inst36|Addr2SRAM[16] at LC_X8_Y4_N8
--operation mode is normal

N1_Addr2SRAM[16]_lut_out = N1_Addr2SRAM[16] & (N1L461 & N1L28 # !N1L38) # !N1_Addr2SRAM[16] & N1L461 & N1L28;
N1_Addr2SRAM[16] = DFFEA(N1_Addr2SRAM[16]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[15] is SRAMInterface:inst36|Addr2SRAM[15] at LC_X8_Y4_N9
--operation mode is normal

N1_Addr2SRAM[15]_lut_out = N1L28 & (N1L061 # N1_Addr2SRAM[15] & !N1L38) # !N1L28 & N1_Addr2SRAM[15] & !N1L38;
N1_Addr2SRAM[15] = DFFEA(N1_Addr2SRAM[15]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[14] is SRAMInterface:inst36|Addr2SRAM[14] at LC_X8_Y4_N0
--operation mode is normal

N1_Addr2SRAM[14]_lut_out = N1L28 & (N1L651 # N1_Addr2SRAM[14] & !N1L38) # !N1L28 & N1_Addr2SRAM[14] & !N1L38;
N1_Addr2SRAM[14] = DFFEA(N1_Addr2SRAM[14]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[13] is SRAMInterface:inst36|Addr2SRAM[13] at LC_X7_Y4_N9
--operation mode is normal

N1_Addr2SRAM[13]_lut_out = N1L28 & (N1L251 # !N1L38 & N1_Addr2SRAM[13]) # !N1L28 & !N1L38 & N1_Addr2SRAM[13];
N1_Addr2SRAM[13] = DFFEA(N1_Addr2SRAM[13]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[12] is SRAMInterface:inst36|Addr2SRAM[12] at LC_X8_Y4_N2
--operation mode is normal

N1_Addr2SRAM[12]_lut_out = N1L28 & (N1L051 # N1_Addr2SRAM[12] & !N1L38) # !N1L28 & N1_Addr2SRAM[12] & !N1L38;
N1_Addr2SRAM[12] = DFFEA(N1_Addr2SRAM[12]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[11] is SRAMInterface:inst36|Addr2SRAM[11] at LC_X8_Y4_N3
--operation mode is normal

N1_Addr2SRAM[11]_lut_out = N1L28 & (N1L641 # N1_Addr2SRAM[11] & !N1L38) # !N1L28 & N1_Addr2SRAM[11] & !N1L38;
N1_Addr2SRAM[11] = DFFEA(N1_Addr2SRAM[11]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[10] is SRAMInterface:inst36|Addr2SRAM[10] at LC_X8_Y4_N6
--operation mode is normal

N1_Addr2SRAM[10]_lut_out = N1L28 & (N1L241 # N1_Addr2SRAM[10] & !N1L38) # !N1L28 & N1_Addr2SRAM[10] & !N1L38;
N1_Addr2SRAM[10] = DFFEA(N1_Addr2SRAM[10]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[9] is SRAMInterface:inst36|Addr2SRAM[9] at LC_X8_Y4_N4
--operation mode is normal

N1_Addr2SRAM[9]_lut_out = N1_Addr2SRAM[9] & (N1L831 & N1L28 # !N1L38) # !N1_Addr2SRAM[9] & N1L831 & N1L28;
N1_Addr2SRAM[9] = DFFEA(N1_Addr2SRAM[9]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[8] is SRAMInterface:inst36|Addr2SRAM[8] at LC_X7_Y5_N5
--operation mode is normal

N1_Addr2SRAM[8]_lut_out = N1L431 & (N1L58 # N1_Addr2SRAM[8] & N1L48) # !N1L431 & N1_Addr2SRAM[8] & N1L48;
N1_Addr2SRAM[8] = DFFEA(N1_Addr2SRAM[8]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[7] is SRAMInterface:inst36|Addr2SRAM[7] at LC_X7_Y5_N9
--operation mode is normal

N1_Addr2SRAM[7]_lut_out = N1L231 & (N1L58 # N1_Addr2SRAM[7] & N1L48) # !N1L231 & N1_Addr2SRAM[7] & N1L48;
N1_Addr2SRAM[7] = DFFEA(N1_Addr2SRAM[7]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[6] is SRAMInterface:inst36|Addr2SRAM[6] at LC_X7_Y5_N3
--operation mode is normal

N1_Addr2SRAM[6]_lut_out = N1_Addr2SRAM[6] & (N1L821 & N1L28 # !N1L38) # !N1_Addr2SRAM[6] & N1L821 & N1L28;
N1_Addr2SRAM[6] = DFFEA(N1_Addr2SRAM[6]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[5] is SRAMInterface:inst36|Addr2SRAM[5] at LC_X7_Y5_N2
--operation mode is normal

N1_Addr2SRAM[5]_lut_out = N1L421 & (N1L28 # N1_Addr2SRAM[5] & !N1L38) # !N1L421 & N1_Addr2SRAM[5] & !N1L38;
N1_Addr2SRAM[5] = DFFEA(N1_Addr2SRAM[5]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[4] is SRAMInterface:inst36|Addr2SRAM[4] at LC_X6_Y4_N1
--operation mode is normal

N1_Addr2SRAM[4]_lut_out = N1L021 & (N1L28 # N1_Addr2SRAM[4] & !N1L38) # !N1L021 & N1_Addr2SRAM[4] & !N1L38;
N1_Addr2SRAM[4] = DFFEA(N1_Addr2SRAM[4]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[3] is SRAMInterface:inst36|Addr2SRAM[3] at LC_X6_Y4_N0
--operation mode is normal

N1_Addr2SRAM[3]_lut_out = N1L611 & (N1L28 # N1_Addr2SRAM[3] & !N1L38) # !N1L611 & N1_Addr2SRAM[3] & !N1L38;
N1_Addr2SRAM[3] = DFFEA(N1_Addr2SRAM[3]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[2] is SRAMInterface:inst36|Addr2SRAM[2] at LC_X6_Y5_N8
--operation mode is normal

N1_Addr2SRAM[2]_lut_out = N1L28 & (N1L411 # N1_Addr2SRAM[2] & !N1L38) # !N1L28 & N1_Addr2SRAM[2] & !N1L38;
N1_Addr2SRAM[2] = DFFEA(N1_Addr2SRAM[2]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[1] is SRAMInterface:inst36|Addr2SRAM[1] at LC_X6_Y5_N6
--operation mode is normal

N1_Addr2SRAM[1]_lut_out = N1_Addr2SRAM[1] & (N1L011 & N1L28 # !N1L38) # !N1_Addr2SRAM[1] & N1L011 & N1L28;
N1_Addr2SRAM[1] = DFFEA(N1_Addr2SRAM[1]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_Addr2SRAM[0] is SRAMInterface:inst36|Addr2SRAM[0] at LC_X6_Y5_N7
--operation mode is normal

N1_Addr2SRAM[0]_lut_out = N1L601 & (N1L28 # N1_Addr2SRAM[0] & !N1L38) # !N1L601 & N1_Addr2SRAM[0] & !N1L38;
N1_Addr2SRAM[0] = DFFEA(N1_Addr2SRAM[0]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1L15Q is SRAMInterface:inst36|NextState~55 at LC_X7_Y7_N9
--operation mode is normal

N1L15Q_lut_out = N1L36 # N1L46 # N1L26;
N1L15Q = DFFEA(N1L15Q_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_num_clks[1] is SRAMInterface:inst36|num_clks[1] at LC_X5_Y7_N3
--operation mode is normal

N1_num_clks[1]_lut_out = N1_num_clks[1] & (N1L081 # !N1_num_clks[0] & !N1L67) # !N1_num_clks[1] & N1_num_clks[0] & !N1L67;
N1_num_clks[1] = DFFEA(N1_num_clks[1]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_num_clks[0] is SRAMInterface:inst36|num_clks[0] at LC_X5_Y6_N5
--operation mode is normal

N1_num_clks[0]_lut_out = N1_num_clks[0] & N1L081 # !N1_num_clks[0] & !N1L67;
N1_num_clks[0] = DFFEA(N1_num_clks[0]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1_num_clks[2] is SRAMInterface:inst36|num_clks[2] at LC_X5_Y7_N9
--operation mode is normal

N1_num_clks[2]_lut_out = N1_num_clks[2] & (N1L081 # N1L25Q $ N1L86) # !N1_num_clks[2] & N1L25Q & N1L86;
N1_num_clks[2] = DFFEA(N1_num_clks[2]_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1L83 is SRAMInterface:inst36|NextState~30 at LC_X5_Y7_N5
--operation mode is normal

N1L83 = N1_num_clks[1] & N1_num_clks[0] & N1L15Q & !N1_num_clks[2];


--N1L14Q is SRAMInterface:inst36|NextState~43 at LC_X5_Y5_N3
--operation mode is normal

N1L14Q_lut_out = N1L37 # N1_USBDataPresent_nRegb & N1L24Q & !Q1_USBCanWrite_nRegb;
N1L14Q = DFFEA(N1L14Q_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1L93Q is SRAMInterface:inst36|NextState~41 at LC_X6_Y5_N9
--operation mode is normal

N1L93Q_lut_out = !N1L16 & !N1L06 & (N1L171 # !N1L04Q);
N1L93Q = DFFEA(N1L93Q_lut_out, GLOBAL(D1_HalfClock), VCC, , , , );


--N1L07 is SRAMInterface:inst36|Select~11898 at LC_X7_Y6_N6
--operation mode is normal