📄 usbrefdesign.fit.rpt
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+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 4.67) ; Number of LABs (Total = 3) ;
+--------------------------------------------+-----------------------------+
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 1.33) ; Number of LABs (Total = 3) ;
+------------------------------------+-----------------------------+
; 1 Clock ; 3 ;
; 1 Clock enable ; 1 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 5.00) ; Number of LABs (Total = 3) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 4.00) ; Number of LABs (Total = 3) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 5.33) ; Number of LABs (Total = 3) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
+---------------------------------------------+-----------------------------+
+--------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+---------------------+
; Option ; Setting ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; On ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+---------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Mon Jun 09 13:17:18 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off USBRefDesign -c USBRefDesign
Info: Selected device EPM1270T144C5 for design "USBRefDesign"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
Info: Pin ~DEV_CLRn~ is reserved at location 61
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "sclk" to use Global clock in PIN 18
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 4.444 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y10; Fanout = 3; REG Node = 'TX_state.TX_state1'
Info: 2: + IC(0.445 ns) + CELL(0.914 ns) = 1.359 ns; Loc. = LAB_X8_Y10; Fanout = 8; COMB Node = 'LED[0]~279'
Info: 3: + IC(1.842 ns) + CELL(1.243 ns) = 4.444 ns; Loc. = LAB_X6_Y10; Fanout = 1; REG Node = 'LED[7]~reg0'
Info: Total cell delay = 2.157 ns ( 48.54 % )
Info: Total interconnect delay = 2.287 ns ( 51.46 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
Info: The peak interconnect region extends from location X0_Y0 to location X8_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin USB_SI has VCC driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Allocated 157 megabytes of memory during processing
Info: Processing ended: Mon Jun 09 13:17:22 2008
Info: Elapsed time: 00:00:04
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/ylc627/QuartusProject/USBRefDesign.fit.smsg.
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