usbrefdesign.map.rpt

这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序

;     -- Combinational with a register        ; 4     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 1     ;
;     -- 3 input functions                    ; 1     ;
;     -- 2 input functions                    ; 3     ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 15    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 13    ;
; I/O pins                                    ; 20    ;
; Maximum fan-out node                        ; sclk  ;
; Maximum fan-out                             ; 13    ;
; Total fan-out                               ; 53    ;
; Average fan-out                             ; 1.51  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |USBRefDesign              ; 15 (15)     ; 13           ; 0          ; 20   ; 0            ; 2 (2)        ; 9 (9)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |USBRefDesign       ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------+
; State Machine - |USBRefDesign|TX_state                                                                 ;
+--------------------+--------------------+--------------------+--------------------+--------------------+
; Name               ; TX_state.TX_state1 ; TX_state.TX_state3 ; TX_state.TX_state2 ; TX_state.TX_state0 ;
+--------------------+--------------------+--------------------+--------------------+--------------------+
; TX_state.TX_state0 ; 0                  ; 0                  ; 0                  ; 0                  ;
; TX_state.TX_state2 ; 0                  ; 0                  ; 1                  ; 1                  ;
; TX_state.TX_state3 ; 0                  ; 1                  ; 0                  ; 1                  ;
; TX_state.TX_state1 ; 1                  ; 0                  ; 0                  ; 1                  ;
+--------------------+--------------------+--------------------+--------------------+--------------------+


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; TX_state~21                           ; Lost fanout        ;
; TX_state~22                           ; Lost fanout        ;
; Total Number of Removed Registers = 2 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 13    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |USBRefDesign ;
+----------------+-------+-----------------------------------------------------+
; Parameter Name ; Value ; Type                                                ;
+----------------+-------+-----------------------------------------------------+
; TX_state0      ; 00    ; Unsigned Binary                                     ;
; TX_state1      ; 01    ; Unsigned Binary                                     ;
; TX_state2      ; 10    ; Unsigned Binary                                     ;
; TX_state3      ; 11    ; Unsigned Binary                                     ;
+----------------+-------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Mon Jun 09 13:17:15 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off USBRefDesign -c USBRefDesign
Info: Found 1 design units, including 1 entities, in source file USBRefDesign.v
    Info: Found entity 1: USBRefDesign
Info: Elaborating entity "USBRefDesign" for the top level hierarchy
Info: State machine "|USBRefDesign|TX_state" contains 4 states
Info: Selected One-Hot state machine encoding method for state machine "|USBRefDesign|TX_state"
Info: Encoding result for state machine "|USBRefDesign|TX_state"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "TX_state.TX_state1"
        Info: Encoded state bit "TX_state.TX_state3"
        Info: Encoded state bit "TX_state.TX_state2"
        Info: Encoded state bit "TX_state.TX_state0"
    Info: State "|USBRefDesign|TX_state.TX_state0" uses code string "0000"
    Info: State "|USBRefDesign|TX_state.TX_state2" uses code string "0011"
    Info: State "|USBRefDesign|TX_state.TX_state3" uses code string "0101"
    Info: State "|USBRefDesign|TX_state.TX_state1" uses code string "1001"
Warning: Hierarchy name "DivideClock:inst5" does not exist.  It is associated with user assignments.
Warning: Hierarchy name "SRAMInterface:inst36" does not exist.  It is associated with user assignments.
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "USB_SI" stuck at VCC
Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
    Info: Register "TX_state~21" lost all its fanouts during netlist optimizations.
    Info: Register "TX_state~22" lost all its fanouts during netlist optimizations.
Info: Implemented 35 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 10 output pins
    Info: Implemented 15 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Allocated 124 megabytes of memory during processing
    Info: Processing ended: Mon Jun 09 13:17:17 2008
    Info: Elapsed time: 00:00:02