_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity top_stepper is
    port(
        a_high          : out    vl_logic;
        a_low           : out    vl_logic;
        b_high          : out    vl_logic;
        b_low           : out    vl_logic;
        c_high          : out    vl_logic;
        c_low           : out    vl_logic;
        d_high          : out    vl_logic;
        d_low           : out    vl_logic;
        step_rpm_ctrl   : out    vl_logic_vector(3 downto 0);
        run_signal      : out    vl_logic;
        step_signal     : out    vl_logic;
        dc_ch_clk_8     : in     vl_logic;
        dc_ch_clk_16    : in     vl_logic;
        low_rng_clk     : in     vl_logic;
        high_rng_clk    : in     vl_logic;
        plus            : in     vl_logic;
        minus           : in     vl_logic;
        range_select_sw : in     vl_logic;
        cw_or_ccw       : in     vl_logic;
        run             : in     vl_logic;
        stop            : in     vl_logic;
        step            : in     vl_logic;
        sel_step_mode   : in     vl_logic_vector(1 downto 0);
        microstep_16_or_8: in     vl_logic;
        microstep_on_off: in     vl_logic;
        clk_8microstep  : in     vl_logic;
        clk_16microstep : in     vl_logic;
        sys_clk         : in     vl_logic;
        rst_l           : in     vl_logic
    );
end top_stepper;