_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity stepper_ip is
    port(
        PHASEA_H        : out    vl_logic;
        PHASEA_L        : out    vl_logic;
        PHASEB_H        : out    vl_logic;
        PHASEB_L        : out    vl_logic;
        PHASEC_H        : out    vl_logic;
        PHASEC_L        : out    vl_logic;
        PHASED_H        : out    vl_logic;
        PHASED_L        : out    vl_logic;
        clk_76hz        : out    vl_logic;
        stp_run_signal  : out    vl_logic;
        rpm_value       : out    vl_logic_vector(7 downto 0);
        run             : in     vl_logic;
        stop            : in     vl_logic;
        plus            : in     vl_logic;
        minus           : in     vl_logic;
        step            : in     vl_logic;
        cw_or_ccw       : in     vl_logic;
        mst_or_bd_bl    : in     vl_logic;
        stepper_range   : in     vl_logic;
        full_half_or_cad: in     vl_logic;
        mstp_or_bl_md   : in     vl_logic;
        sys_clk         : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        rst_l           : in     vl_logic
    );
end stepper_ip;