_primary.vhd

来自「步进电机 VHDL 控制」· VHDL 代码 · 共 37 行

library verilog;
use verilog.vl_types.all;
entity serial is
    generic(
        CTR0_MOTOR      : integer := 0;
        CTR1_MOTOR      : integer := 1;
        CTR2_MOTOR      : integer := 2;
        CTR3_MOTOR      : integer := 3;
        CTR4_MOTOR      : integer := 4;
        CTR5_MOTOR      : integer := 5;
        CTR6_MOTOR      : integer := 6;
        CTR7_MOTOR      : integer := 7
    );
    port(
        MSTP_OR_BL_MD_S : out    vl_logic;
        MST_OR_BD_BL_S  : out    vl_logic;
        RUN_S           : out    vl_logic;
        STOP_S          : out    vl_logic;
        CW_OR_CCW_S     : out    vl_logic;
        STEPPER_RNG_S   : out    vl_logic;
        FULL_OR_HALF_S  : out    vl_logic;
        PLUS_S          : out    vl_logic;
        MINUS_S         : out    vl_logic;
        STEP_S          : out    vl_logic;
        STEPPER_OR_BDBL_S: out    vl_logic;
        SYS_RST_S       : out    vl_logic;
        trans_trig      : out    vl_logic;
        tx_data         : out    vl_logic_vector(6 downto 0);
        rx_data         : in     vl_logic_vector(7 downto 0);
        data_recv       : in     vl_logic;
        load_shift      : in     vl_logic;
        set_ri          : in     vl_logic;
        sys_clk         : in     vl_logic;
        rst_l           : in     vl_logic
    );
end serial;