_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity stepper_module is
    port(
        a_high          : out    vl_logic;
        a_low           : out    vl_logic;
        b_high          : out    vl_logic;
        b_low           : out    vl_logic;
        c_high          : out    vl_logic;
        c_low           : out    vl_logic;
        d_high          : out    vl_logic;
        d_low           : out    vl_logic;
        r_edge_seq_done : out    vl_logic;
        step_signal     : out    vl_logic;
        run_signal      : out    vl_logic;
        rst_stop_sig_l  : out    vl_logic;
        count_set       : out    vl_logic_vector(2 downto 0);
        stepper_clk     : in     vl_logic;
        cw_or_ccw       : in     vl_logic;
        run             : in     vl_logic;
        stop            : in     vl_logic;
        step            : in     vl_logic;
        sel_step_mode   : in     vl_logic_vector(1 downto 0);
        pwm_out         : in     vl_logic;
        pwm_out1        : in     vl_logic;
        sys_clk         : in     vl_logic;
        rst_l           : in     vl_logic
    );
end stepper_module;