_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity pwm_gen_stepper is
    port(
        pwm_out         : out    vl_logic;
        pwm_out1        : out    vl_logic;
        step_rpm_final  : in     vl_logic_vector(3 downto 0);
        count_set       : in     vl_logic_vector(2 downto 0);
        start           : in     vl_logic;
        rst_stop_sig_l  : in     vl_logic;
        microstep_16_or_8: in     vl_logic;
        step_signal     : in     vl_logic;
        dc_ch_clk_8     : in     vl_logic;
        dc_ch_clk_16    : in     vl_logic;
        clk_8microstep  : in     vl_logic;
        clk_16microstep : in     vl_logic;
        sys_clk         : in     vl_logic;
        rst_l           : in     vl_logic
    );
end pwm_gen_stepper;