_primary.vhd

来自「步进电机 VHDL 控制」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity xmit_control is
    port(
        TXD             : out    vl_logic;
        load_shift      : out    vl_logic;
        tx_data         : in     vl_logic_vector(6 downto 0);
        trans_trig      : in     vl_logic;
        tx_clk          : in     vl_logic;
        sys_clk         : in     vl_logic;
        rst_l           : in     vl_logic
    );
end xmit_control;