_primary.vhd

来自「步进电机 VHDL 控制」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity debounce is
    port(
        debounce_out    : out    vl_logic;
        debounce_in     : in     vl_logic;
        sys_clk         : in     vl_logic;
        debounce_clk_in : in     vl_logic;
        rst_l           : in     vl_logic
    );
end debounce;