_primary.vhd

来自「步进电机 VHDL 控制」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity clk_by_2 is
    port(
        out_clock       : out    vl_logic;
        out_clock_b     : out    vl_logic;
        reset_l         : in     vl_logic;
        in_clock        : in     vl_logic
    );
end clk_by_2;