_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity stepper_clk_gen is
    port(
        stepper_clk     : out    vl_logic;
        step_rpm_ctrl   : out    vl_logic_vector(3 downto 0);
        step_rpm_final  : out    vl_logic_vector(3 downto 0);
        run_signal      : in     vl_logic;
        range_select_sw : in     vl_logic;
        step_signal     : in     vl_logic;
        rst_stop_sig_l  : in     vl_logic;
        high_rng_clk    : in     vl_logic;
        low_rng_clk     : in     vl_logic;
        microstep_on_off: in     vl_logic;
        r_edge_seq_done : in     vl_logic;
        plus            : in     vl_logic;
        minus           : in     vl_logic;
        sys_clk         : in     vl_logic;
        rst_l           : in     vl_logic
    );
end stepper_clk_gen;