_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity mux_hw_sw is
    port(
        rst_l           : out    vl_logic;
        mstp_or_bl_md   : out    vl_logic;
        stepper_range   : out    vl_logic;
        full_half_or_cad: out    vl_logic;
        run             : out    vl_logic;
        stop            : out    vl_logic;
        cw_or_ccw       : out    vl_logic;
        plus            : out    vl_logic;
        minus           : out    vl_logic;
        step            : out    vl_logic;
        mst_or_bd_bl    : out    vl_logic;
        SYS_RESET       : in     vl_logic;
        HW_SW           : in     vl_logic;
        MSTP_OR_BL_MD_H : in     vl_logic;
        STEPPER_RNG_H   : in     vl_logic;
        full_half_or_cad_h_db: in     vl_logic;
        run_h_db        : in     vl_logic;
        stop_h_db       : in     vl_logic;
        cw_or_ccw_h_db  : in     vl_logic;
        plus_h_db       : in     vl_logic;
        minus_h_db      : in     vl_logic;
        step_h_db       : in     vl_logic;
        mst_or_bd_bl_h_db: in     vl_logic;
        MSTP_OR_BL_MD_S : in     vl_logic;
        MST_OR_BD_BL_S  : in     vl_logic;
        RUN_S           : in     vl_logic;
        STOP_S          : in     vl_logic;
        CW_OR_CCW_S     : in     vl_logic;
        STEPPER_RNG_S   : in     vl_logic;
        FULL_OR_HALF_S  : in     vl_logic;
        PLUS_S          : in     vl_logic;
        MINUS_S         : in     vl_logic;
        STEP_S          : in     vl_logic;
        SYS_RST         : in     vl_logic
    );
end mux_hw_sw;