_primary.vhd

来自「步进电机 VHDL 控制」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity debounce_1_5 is
    port(
        debounce_out_0_sqmuxa: in     vl_logic;
        cw_or_ccw_h_db  : out    vl_logic;
        debounce_out_1_sqmuxa: in     vl_logic;
        CW_OR_CCW_H_c   : in     vl_logic;
        rst_l           : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        switch_in_reg   : out    vl_logic
    );
end debounce_1_5;