_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity clk_gen is
    port(
        debounce_clk    : out    vl_logic;
        rst_l           : in     vl_logic;
        clk_600hz       : out    vl_logic;
        clk_300hz       : out    vl_logic;
        clk_10mhz       : in     vl_logic;
        clk_5mhz        : out    vl_logic;
        clk_19khz       : out    vl_logic;
        clk_39khz       : out    vl_logic
    );
end clk_gen;