_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity top_stepper is
    port(
        clk_300hz       : in     vl_logic;
        clk_600hz       : in     vl_logic;
        stp_rng_sel     : in     vl_logic;
        minus           : in     vl_logic;
        plus            : in     vl_logic;
        stp_run_signal_0: out    vl_logic;
        run_signal      : out    vl_logic;
        un16_stp_sel_mode: in     vl_logic;
        stp_microstep_0 : in     vl_logic;
        stp_cw_or_ccw_0 : in     vl_logic;
        run             : in     vl_logic;
        step            : in     vl_logic;
        stp_cw_or_ccw   : in     vl_logic;
        stp_microstep   : in     vl_logic;
        stop            : in     vl_logic;
        PHASEC_H_c      : out    vl_logic;
        PHASED_H_c      : out    vl_logic;
        PHASED_L_c      : out    vl_logic;
        PHASEC_L_c      : out    vl_logic;
        PHASEB_L_c      : out    vl_logic;
        PHASEA_L_c      : out    vl_logic;
        PHASEA_H_c      : out    vl_logic;
        PHASEB_H_c      : out    vl_logic;
        clk_10mhz       : in     vl_logic;
        stp_micro_16_or_8_0: in     vl_logic;
        un1_run_signal  : out    vl_logic;
        stp_micro_16_or_8: in     vl_logic;
        clk_19khz       : in     vl_logic;
        clk_39khz       : in     vl_logic;
        clk_5mhz        : in     vl_logic;
        rst_l           : in     vl_logic
    );
end top_stepper;