_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity stepper_ip is
    port(
        debounce_clk    : out    vl_logic;
        rst_l           : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        PHASEB_H_c      : out    vl_logic;
        PHASEA_H_c      : out    vl_logic;
        PHASEA_L_c      : out    vl_logic;
        PHASEB_L_c      : out    vl_logic;
        PHASEC_L_c      : out    vl_logic;
        PHASED_L_c      : out    vl_logic;
        PHASED_H_c      : out    vl_logic;
        PHASEC_H_c      : out    vl_logic;
        stop            : in     vl_logic;
        step            : in     vl_logic;
        run             : in     vl_logic;
        plus            : in     vl_logic;
        minus           : in     vl_logic;
        full_half_or_cad: in     vl_logic;
        stepper_range   : in     vl_logic;
        mstp_or_bl_md   : in     vl_logic;
        mst_or_bd_bl    : in     vl_logic;
        cw_or_ccw       : in     vl_logic
    );
end stepper_ip;