_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity top_stepper_ip is
    port(
        TXD             : out    vl_logic;
        PHASEA_H        : out    vl_logic;
        PHASEA_L        : out    vl_logic;
        PHASEB_H        : out    vl_logic;
        PHASEB_L        : out    vl_logic;
        PHASEC_H        : out    vl_logic;
        PHASEC_L        : out    vl_logic;
        PHASED_H        : out    vl_logic;
        PHASED_L        : out    vl_logic;
        HW_SW           : in     vl_logic;
        MSTP_OR_BL_MD_H : in     vl_logic;
        STEPPER_RNG_H   : in     vl_logic;
        FULL_HALF_OR_CAD_H: in     vl_logic;
        RUN_H           : in     vl_logic;
        STOP_H          : in     vl_logic;
        CW_OR_CCW_H     : in     vl_logic;
        PLUS_H          : in     vl_logic;
        MINUS_H         : in     vl_logic;
        STEP_H          : in     vl_logic;
        MST_OR_BD_BL_H  : in     vl_logic;
        RXD             : in     vl_logic;
        SYS_CLK         : in     vl_logic;
        SYS_RESET       : in     vl_logic
    );
end top_stepper_ip;