_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity baud_clk_gen is
    port(
        baud_clk_i      : out    vl_logic;
        baud_clk        : out    vl_logic;
        SYS_RESET_c     : in     vl_logic;
        clk_10mhz       : in     vl_logic
    );
end baud_clk_gen;