_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity debounce_1_7 is
    port(
        mst_or_bd_bl_h_db: out    vl_logic;
        debounce_clk    : in     vl_logic;
        rst_l           : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        clk_in_i        : out    vl_logic;
        MST_OR_BD_BL_H_c: in     vl_logic;
        debounce_out_1_sqmuxa_1: out    vl_logic;
        switch_in_reg_1 : in     vl_logic;
        FULL_HALF_OR_CAD_H_c: in     vl_logic;
        debounce_out_0_sqmuxa_1: out    vl_logic;
        debounce_out_1_sqmuxa_0: out    vl_logic;
        switch_in_reg_0 : in     vl_logic;
        CW_OR_CCW_H_c   : in     vl_logic;
        debounce_out_0_sqmuxa_0: out    vl_logic;
        debounce_out_1_sqmuxa: out    vl_logic;
        switch_in_reg   : in     vl_logic;
        STEP_H_c        : in     vl_logic;
        debounce_out_0_sqmuxa: out    vl_logic;
        clk_in          : out    vl_logic;
        sync_clk_in_i   : in     vl_logic
    );
end debounce_1_7;