_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity clk_by_2_25 is
    port(
        SYS_RESET_c     : in     vl_logic;
        in_clk_div_by_32: in     vl_logic;
        baud_clk        : out    vl_logic;
        baud_clk_i      : out    vl_logic
    );
end clk_by_2_25;