_primary.vhd

来自「步进电机 VHDL 控制」· VHDL 代码 · 共 25 行

library verilog;
use verilog.vl_types.all;
entity debounce_1_3 is
    port(
        stop_h_db       : out    vl_logic;
        rst_l           : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        STOP_H_c        : in     vl_logic;
        debounce_out_1_sqmuxa_1: out    vl_logic;
        switch_in_reg_1 : in     vl_logic;
        RUN_H_c         : in     vl_logic;
        debounce_out_0_sqmuxa_1: out    vl_logic;
        debounce_out_1_sqmuxa_0: out    vl_logic;
        switch_in_reg_0 : in     vl_logic;
        PLUS_H_c        : in     vl_logic;
        debounce_out_0_sqmuxa_0: out    vl_logic;
        debounce_out_1_sqmuxa: out    vl_logic;
        switch_in_reg   : in     vl_logic;
        MINUS_H_c       : in     vl_logic;
        debounce_out_0_sqmuxa: out    vl_logic;
        clk_in          : in     vl_logic;
        sync_clk_in_i   : in     vl_logic
    );
end debounce_1_3;