_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity clk_by_2_2 is
    port(
        rst_l           : in     vl_logic;
        in_clk_div_by_4 : in     vl_logic;
        div_by_4_i      : out    vl_logic
    );
end clk_by_2_2;