_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity serial is
    port(
        tx_data         : out    vl_logic_vector(6 downto 0);
        rx_data_0       : in     vl_logic_vector(6 downto 5);
        rx_data         : in     vl_logic_vector(7 downto 0);
        RUN_S           : out    vl_logic;
        MSTP_OR_BL_MD_S : out    vl_logic;
        MST_OR_BD_BL_S  : out    vl_logic;
        STEPPER_RNG_S   : out    vl_logic;
        FULL_OR_HALF_S  : out    vl_logic;
        CW_OR_CCW_S     : out    vl_logic;
        STEP_S          : out    vl_logic;
        MINUS_S         : out    vl_logic;
        PLUS_S          : out    vl_logic;
        STOP_S          : out    vl_logic;
        clk_10mhz       : in     vl_logic;
        load_shift      : in     vl_logic;
        set_ri          : in     vl_logic;
        SYS_RESET_c     : in     vl_logic;
        trans_trig      : out    vl_logic;
        sync2_set_ri_i  : in     vl_logic;
        sync1_set_ri    : in     vl_logic;
        data_recv       : in     vl_logic;
        SYS_RST         : out    vl_logic
    );
end serial;