_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity stepper_module is
    port(
        count_set_1     : out    vl_logic;
        rst_stop_l      : in     vl_logic;
        rst_stop_sig_l  : out    vl_logic;
        PHASEB_H_c      : out    vl_logic;
        PHASEA_H_c      : out    vl_logic;
        PHASEA_L_c      : out    vl_logic;
        PHASEB_L_c      : out    vl_logic;
        PHASEC_L_c      : out    vl_logic;
        PHASED_L_c      : out    vl_logic;
        PHASED_H_c      : out    vl_logic;
        PHASEC_H_c      : out    vl_logic;
        stepper_clk     : in     vl_logic;
        stop            : in     vl_logic;
        stp_microstep   : in     vl_logic;
        stp_cw_or_ccw   : in     vl_logic;
        r_edge_seq_done : out    vl_logic;
        stp_step_signal : out    vl_logic;
        step            : in     vl_logic;
        run             : in     vl_logic;
        pwm_out         : in     vl_logic;
        nxt_A_high_int_3_sqmuxa_1_1: out    vl_logic;
        stp_cw_or_ccw_0 : in     vl_logic;
        stp_microstep_0 : in     vl_logic;
        un16_stp_sel_mode: in     vl_logic;
        rst_l           : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        run_signal      : out    vl_logic;
        stp_run_signal_0: out    vl_logic
    );
end stepper_module;