_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity top_serial is
    port(
        RXD_c           : in     vl_logic;
        TXD_c           : out    vl_logic;
        SYS_RST         : out    vl_logic;
        SYS_RESET_c     : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        STOP_S          : out    vl_logic;
        PLUS_S          : out    vl_logic;
        MINUS_S         : out    vl_logic;
        STEP_S          : out    vl_logic;
        CW_OR_CCW_S     : out    vl_logic;
        FULL_OR_HALF_S  : out    vl_logic;
        STEPPER_RNG_S   : out    vl_logic;
        MST_OR_BD_BL_S  : out    vl_logic;
        MSTP_OR_BL_MD_S : out    vl_logic;
        RUN_S           : out    vl_logic
    );
end top_serial;