_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity pwm_gen_stepper is
    port(
        count_set       : in     vl_logic_vector(1 downto 1);
        step_rpm_final  : in     vl_logic_vector(3 downto 0);
        pwm_out         : out    vl_logic;
        rst_l           : in     vl_logic;
        clk_5mhz        : in     vl_logic;
        clk_39khz       : in     vl_logic;
        clk_19khz       : in     vl_logic;
        stp_micro_16_or_8: in     vl_logic;
        stepper_clk6    : in     vl_logic;
        nxt_A_high_int_3_sqmuxa_1_1: in     vl_logic;
        un1_run_signal  : in     vl_logic;
        stp_micro_16_or_8_0: in     vl_logic;
        rst_stop_l      : in     vl_logic;
        clk_10mhz       : in     vl_logic
    );
end pwm_gen_stepper;