_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity xmit_control is
    port(
        tx_data         : in     vl_logic_vector(6 downto 0);
        TXD_c           : out    vl_logic;
        SYS_RESET_c     : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        trans_trig      : in     vl_logic;
        load_shift      : out    vl_logic;
        tx_clk          : in     vl_logic
    );
end xmit_control;