_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity debounce_blk is
    port(
        MST_OR_BD_BL_H_c: in     vl_logic;
        debounce_clk    : in     vl_logic;
        mst_or_bd_bl_h_db: out    vl_logic;
        FULL_HALF_OR_CAD_H_c: in     vl_logic;
        full_half_or_cad_h_db: out    vl_logic;
        CW_OR_CCW_H_c   : in     vl_logic;
        cw_or_ccw_h_db  : out    vl_logic;
        STEP_H_c        : in     vl_logic;
        step_h_db       : out    vl_logic;
        STOP_H_c        : in     vl_logic;
        stop_h_db       : out    vl_logic;
        RUN_H_c         : in     vl_logic;
        run_h_db        : out    vl_logic;
        PLUS_H_c        : in     vl_logic;
        plus_h_db       : out    vl_logic;
        clk_10mhz       : in     vl_logic;
        rst_l           : in     vl_logic;
        MINUS_H_c       : in     vl_logic;
        minus_h_db      : out    vl_logic
    );
end debounce_blk;