_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity div_by_16 is
    port(
        tx_clk          : out    vl_logic;
        r_edge_baud_clk : in     vl_logic;
        SYS_RESET_c     : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        sync_baud_clk_i : in     vl_logic;
        baud_clk        : in     vl_logic
    );
end div_by_16;