_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity recv_control is
    port(
        rx_data         : out    vl_logic_vector(7 downto 0);
        rx_data_0       : out    vl_logic_vector(6 downto 5);
        baud_clk_i      : in     vl_logic;
        baud_clk        : in     vl_logic;
        sync_baud_clk_i : out    vl_logic;
        sync2_set_ri_i  : out    vl_logic;
        data_recv       : out    vl_logic;
        r_edge_baud_clk : out    vl_logic;
        sync1_set_ri    : out    vl_logic;
        SYS_RESET_c     : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        set_ri          : out    vl_logic;
        RXD_c           : in     vl_logic
    );
end recv_control;