_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity clk_by_2 is
    port(
        SYS_RESET_c     : in     vl_logic;
        SYS_CLK_c       : in     vl_logic;
        clk_10mhz       : out    vl_logic
    );
end clk_by_2;