_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity stepper_clk_gen is
    port(
        step_rpm_final  : out    vl_logic_vector(3 downto 0);
        r_edge_seq_done : in     vl_logic;
        stepper_clk     : out    vl_logic;
        plus            : in     vl_logic;
        minus           : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        stp_microstep   : in     vl_logic;
        stp_rng_sel     : in     vl_logic;
        clk_600hz       : in     vl_logic;
        clk_300hz       : in     vl_logic;
        rst_l           : in     vl_logic;
        rst_stop_sig_l  : in     vl_logic;
        rst_stop_l      : out    vl_logic;
        stp_step_signal : in     vl_logic;
        stepper_clk6    : out    vl_logic;
        stp_run_signal_0: in     vl_logic;
        un1_run_signal  : out    vl_logic
    );
end stepper_clk_gen;