_primary.vhd

步进电机 VHDL 控制

library verilog;
use verilog.vl_types.all;
entity debounce_1_6 is
    port(
        debounce_out_0_sqmuxa: in     vl_logic;
        full_half_or_cad_h_db: out    vl_logic;
        debounce_out_1_sqmuxa: in     vl_logic;
        FULL_HALF_OR_CAD_H_c: in     vl_logic;
        rst_l           : in     vl_logic;
        clk_10mhz       : in     vl_logic;
        switch_in_reg   : out    vl_logic
    );
end debounce_1_6;