clksim.map.qmsg

设计实体：lcd驱动器 --彩色液晶芯片LQ080V3DG01 --原创针对博创开发板UP-SOPC2000开发板写的彩色液晶驱动程序

{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "Data_Disp\[8\]\$latch " "Warning: Latch Data_Disp\[8\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st3 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st3" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 48 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "Data_Disp\[9\]\$latch " "Warning: Latch Data_Disp\[9\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st3 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st3" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 48 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "Data_Disp\[10\]\$latch " "Warning: Latch Data_Disp\[10\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st3 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st3" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 48 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "Data_Disp\[11\]\$latch " "Warning: Latch Data_Disp\[11\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st3 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st3" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 48 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "Data_Disp\[12\]\$latch " "Warning: Latch Data_Disp\[12\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st3 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st3" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 48 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "Data_Disp\[13\]\$latch " "Warning: Latch Data_Disp\[13\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st3 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st3" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 48 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "Data_Disp\[14\]\$latch " "Warning: Latch Data_Disp\[14\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st3 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st3" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 48 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "Data_Disp\[15\]\$latch " "Warning: Latch Data_Disp\[15\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st3 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st3" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 48 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addr\[7\] " "Warning: Latch addr\[7\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st2 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st2" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addr\[9\] " "Warning: Latch addr\[9\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st2 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st2" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addr\[4\] " "Warning: Latch addr\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st2 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st2" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addr\[6\] " "Warning: Latch addr\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st2 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st2" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addr\[8\] " "Warning: Latch addr\[8\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st2 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st2" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addr\[5\] " "Warning: Latch addr\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st2 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st2" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addr\[2\] " "Warning: Latch addr\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st2 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st2" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addr\[3\] " "Warning: Latch addr\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st2 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st2" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addr\[0\] " "Warning: Latch addr\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st2 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st2" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addr\[1\] " "Warning: Latch addr\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st2 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st2" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addr\[10\] " "Warning: Latch addr\[10\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA present_state.st2 " "Warning: Ports D and ENA on the latch are fed by the same signal present_state.st2" {  } {  } 0}  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 28 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "ENAB GND " "Warning: Pin \"ENAB\" stuck at GND" {  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 15 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "bit3 " "Warning: No output dependent on input pin \"bit3\"" {  } { { "clksim.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/lcd/时序模拟/clksim.vhd" 11 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "980 " "Info: Implemented 980 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "954 " "Info: Implemented 954 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_DSP_ELEM" "2 " "Info: Implemented 2 DSP elements" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 62 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 62 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 02 14:11:04 2008 " "Info: Processing ended: Mon Jun 02 14:11:04 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:48 " "Info: Elapsed time: 00:01:48" {  } {  } 0}  } {  } 0}