📄 clksim.map.rpt
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; -- Combinational cells for routing ; 0 ;
; Logic elements by mode ; ;
; -- normal mode ; 733 ;
; -- arithmetic mode ; 119 ;
; Total registers ; 102 ;
; I/O pins ; 24 ;
; Embedded Multiplier 9-bit elements ; 2 ;
; Maximum fan-out node ; addr[6] ;
; Maximum fan-out ; 229 ;
; Total fan-out ; 3298 ;
; Average fan-out ; 3.37 ;
+---------------------------------------------+---------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------+
; |clksim ; 852 (852) ; 102 (102) ; 0 ; 2 ; 0 ; 1 ; 24 ; 0 ; |clksim ;
; |lpm_mult:mult_rtl_0| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |clksim|lpm_mult:mult_rtl_0 ;
; |mult_9q01:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |clksim|lpm_mult:mult_rtl_0|mult_9q01:auto_generated ;
+----------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary ;
+---------------------------------------+-------------+
; Statistic ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit) ; 0 ;
; Simple Multipliers (18-bit) ; 1 ;
; Embedded Multiplier Blocks ; -- ;
; Embedded Multiplier 9-bit elements ; 2 ;
; Signed Embedded Multipliers ; 1 ;
; Unsigned Embedded Multipliers ; 0 ;
; Mixed Sign Embedded Multipliers ; 0 ;
; Variable Sign Embedded Multipliers ; 0 ;
; Dedicated Input Shift Register Chains ; 0 ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.
+-------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |clksim|present_state ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name ; present_state.st5 ; present_state.st4 ; present_state.st3 ; present_state.st2 ; present_state.st1 ; present_state.st0 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; present_state.st0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; present_state.st1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; present_state.st2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; present_state.st3 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; present_state.st4 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; present_state.st5 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
+----------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------+----+
; Latch Name ; ;
+-----------------------------------------------+----+
; Data_Disp[0]$latch ; ;
; Data_Disp[1]$latch ; ;
; Data_Disp[2]$latch ; ;
; Data_Disp[3]$latch ; ;
; Data_Disp[4]$latch ; ;
; Data_Disp[5]$latch ; ;
; Data_Disp[6]$latch ; ;
; Data_Disp[7]$latch ; ;
; Data_Disp[8]$latch ; ;
; Data_Disp[9]$latch ; ;
; Data_Disp[10]$latch ; ;
; Data_Disp[11]$latch ; ;
; Data_Disp[12]$latch ; ;
; Data_Disp[13]$latch ; ;
; Data_Disp[14]$latch ; ;
; Data_Disp[15]$latch ; ;
; addr[7] ; ;
; addr[9] ; ;
; addr[4] ; ;
; addr[6] ; ;
; addr[8] ; ;
; addr[5] ; ;
; addr[2] ; ;
; addr[3] ; ;
; addr[0] ; ;
; addr[1] ; ;
; addr[10] ; ;
; Number of user-specified and inferred latches ; 27 ;
+-----------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 102 ;
; Number of registers using Synchronous Clear ; 96 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 38 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 6:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |clksim|frame_control[2] ;
; 2006:1 ; 16 bits ; 21392 LEs ; 13152 LEs ; 8240 LEs ; No ; |clksim|Select~0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_mult:mult_rtl_0 ;
+------------------------------------------------+------------+---------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------------------+------------+---------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTHA ; 7 ; Untyped ;
; LPM_WIDTHB ; 11 ; Untyped ;
; LPM_WIDTHP ; 18 ; Untyped ;
; LPM_WIDTHR ; 18 ; Untyped ;
; LPM_WIDTHS ; 1 ; Untyped ;
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; LATENCY ; 0 ; Untyped ;
; INPUT_A_IS_CONSTANT ; YES ; Untyped ;
; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
; USE_EAB ; OFF ; Untyped ;
; MAXIMIZE_SPEED ; 6 ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; APEX20K_TECHNOLOGY_MAPPER ; Lut ; TECH_MAPPER_APEX20K ;
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