clksim.tan.rpt

来自「设计实体：lcd驱动器 --彩色液晶芯片LQ080V3DG01 --原创针对」· RPT 代码 · 共 331 行 · 第 1/5 页

; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clkin           ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clkin'                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+-----------------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From            ; To              ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[0]  ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[1]  ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[2]  ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[3]  ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[4]  ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[15] ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[12] ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[11] ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[5]  ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[14] ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[13] ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[7]  ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[8]  ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[9]  ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[6]  ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 87.50 MHz ( period = 11.429 ns )                    ; count_Vsync[15] ; count_Vsync[10] ; clkin      ; clkin    ; None                        ; None                      ; 7.881 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[17] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[18] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[16] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[20] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[22] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[21] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[19] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[24] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[26] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[25] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[23] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[27] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[28] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[29] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[30] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 90.96 MHz ( period = 10.994 ns )                    ; count_Vsync[15] ; count_Vsync[31] ; clkin      ; clkin    ; None                        ; None                      ; 7.448 ns                ;
; N/A                                     ; 92.11 MHz ( period = 10.856 ns )                    ; count_Vsync[16] ; count_Vsync[0]  ; clkin      ; clkin    ; None                        ; None                      ; 7.306 ns                ;
; N/A                                     ; 92.11 MHz ( period = 10.856 ns )                    ; count_Vsync[16] ; count_Vsync[1]  ; clkin      ; clkin    ; None                        ; None                      ; 7.306 ns                ;
; N/A                                     ; 92.11 MHz ( period = 10.856 ns )                    ; count_Vsync[16] ; count_Vsync[2]  ; clkin      ; clkin    ; None                        ; None                      ; 7.306 ns                ;
; N/A                                     ; 92.11 MHz ( period = 10.856 ns )                    ; count_Vsync[16] ; count_Vsync[3]  ; clkin      ; clkin    ; None                        ; None                      ; 7.306 ns                ;
; N/A                                     ; 92.11 MHz ( period = 10.856 ns )                    ; count_Vsync[16] ; count_Vsync[4]  ; clkin      ; clkin    ; None                        ; None                      ; 7.306 ns                ;
; N/A                                     ; 92.11 MHz ( period = 10.856 ns )                    ; count_Vsync[16] ; count_Vsync[15] ; clkin      ; clkin    ; None                        ; None                      ; 7.306 ns                ;
; N/A                                     ; 92.11 MHz ( period = 10.856 ns )                    ; count_Vsync[16] ; count_Vsync[12] ; clkin      ; clkin    ; None                        ; None                      ; 7.306 ns                ;
; N/A                                     ; 92.11 MHz ( period = 10.856 ns )                    ; count_Vsync[16] ; count_Vsync[11] ; clkin      ; clkin    ; None                        ; None                      ; 7.306 ns                ;
; N/A                                     ; 92.11 MHz ( period = 10.856 ns )                    ; count_Vsync[16] ; count_Vsync[5]  ; clkin      ; clkin    ; None                        ; None                      ; 7.306 ns                ;
; N/A                                     ; 92.11 MHz ( period = 10.856 ns )                    ; count_Vsync[16] ; count_Vsync[14] ; clkin      ; clkin    ; None                        ; None                      ; 7.306 ns                ;
; N/A                                     ; 92.11 MHz ( period = 10.856 ns )                    ; count_Vsync[16] ; count_Vsync[13] ; clkin      ; clkin    ; None                        ; None                      ; 7.306 ns                ;