lcm.npl

来自「清华大学verilog hdl源码例子」· NPL 代码 · 共 31 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT LCM
DESIGN lcm
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE fpga_lcm.v
SOURCE lcm.v
SOURCE rom_32x8.v
DEPASSOC fpga_lcm fpga_lcm.ucf
DEPASSOC rom_32x8 rom_32x8.ucf
[STATUS-ALL]
fpga_lcm.bitgenGroup=OK,0
rom_32x8.bitgenGroup=OK,0
[STRATEGY-LIST]
Normal=True