bcd3.vhd

来自「实现bcd码与二进制码之间的相互转换功能」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.STD_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY d2 IS
	 PORT(clk:in STD_LOGIC;
	      a,b:in STD_LOGIC_VECTOR(3 downto 0);
	      c:OUT STD_LOGIC_VECTOR(4 downto 0);
	      L,S:OUT STD_LOGIC);
END d2;
ARCHITECTURE one of d2 IS
	  	  BEGIN
  process(a,b)
 variable temp:STD_LOGIC_VECTOR(4 downto 0);
    begin
    TEMP:=('0'&a)+('0'&b);
      if(temp>=19) then temp:="00000";
        l<=clk;
        s<=clk;
        end if;
      if (temp>9) then temp:=temp+6;
		end if;
        c<=temp;
       end process;
      END ARCHITECTURE one;