bcd.vhd

来自「实现bcd码与二进制码之间的相互转换功能」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.STD_logic_unsigned.all;
ENTITY bcd IS
 PORT(clk:in STD_LOGIC;
     a,b:in STD_LOGIC_VECTOR(3 downto 0);
      sum:OUT STD_LOGIC_VECTOR(4 downto 0);
       l:out STD_LOGIC ;
       s :out STD_LOGIC  );
END bcd;
ARCHITECTURE one of bcd IS
 begin
 process(a,b)
 variable temp:STD_LOGIC_VECTOR(4 downto 0);
     begin
     temp:=('0'& a)+('0'& b );
      if (temp>=19)
      then temp:="00000";
     l<=clk;
     s<=clk;
    end  if;
 if(temp>9)
     then temp:=temp + 6;
   end  if;
sum<=temp;
   end process;
    END ARCHITECTURE one;