📄 bcd2.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.STD_logic_unsigned.all;
ENTITY hehee IS
PORT(a,b:in STD_LOGIC_VECTOR(3 downto 0);
sum:OUT STD_LOGIC_VECTOR(4 downto 0));
END hehee;
ARCHITECTURE one of hehee IS
signal temp:STD_LOGIC_VECTOR(4 downto 0);
BEGIN
process(a,b)
begin
temp<=('0'&a)+('0'&b);
if (temp>"10011")then sum<="00000";
elsif (temp<="10011") then sum<= temp + "00110";
else sum<=temp;
end if;
end process;
END ARCHITECTURE one;
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