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<div class="post-nav"><a class="l" href="http://www.dadwj.cn/post/721.html">« VHDL程序与仿真十七---采用等精度测频原理的频率计</a><a class="r" href="http://www.dadwj.cn/post/723.html">VHDL程序与仿真十九---电梯控制器 »</a></div>
<h4 class="post-date">2008-5-17 15:8:40</h4>
<h2 class="post-title">VHDL程序与仿真十八---电子琴</h2>
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</script></DIV><p> </p><div style="text-indent: 21pt"><a href="http://ddwj.net.ru/catalog.asp?cate=7" Class="keylink" title="电子技术" Target="电子技术" >电子</a>琴VHDL程序包含有：顶层程序、音阶发生器程序、数控分频模块程序和自动演奏模块程序<span style="color: black">。</span></div><div><span style="font-size: 12pt">1.</span><span style="font-size: 12pt">顶层程序与仿真</span></div><div>（1）顶层VHDL程序</div><div>--文件名：top.vhd</div><div>--功能：顶层文件</div><div align="left">library IEEE;</div><div align="left">use IEEE.STD_LOGIC_1164.ALL;</div><div align="left">use IEEE.STD_LOGIC_ARITH.ALL;</div><div align="left">use IEEE.STD_LOGIC_UNSIGNED.ALL;</div><div align="left">entity top is</div><div style="text-indent: 10.5pt" align="left">Port ( clk32MHz :in std_logic;<span> --32MHz</span>系统时钟</div><div style="text-indent: 35.9pt" align="left">handTOauto : in std_logic;<span> --</span>键盘输入/自动演奏</div><div style="text-indent: 35.9pt" align="left">code1<span> :out std_logic_vector(6 downto 0); --</span>音符显示信号</div><div style="text-indent: 35.9pt" align="left">index1<span> :in std_logic_vector(7 downto 0); --</span>键盘输入信号</div><div style="text-indent: 35.9pt" align="left">high1<span> :out std_logic; --</span>高低音节信号</div><div style="text-indent: 35.9pt" align="left">spkout<span> :out std_logic); --</span>音频信号</div><div style="text-indent: 10.5pt" align="left">end top;</div><div align="left">architecture Behavioral of top is</div><div align="left">component automusic</div><div style="text-indent: 10.5pt" align="left">Port ( clk :in std_logic;<span> </span></div><div style="text-indent: 35.9pt" align="left">Auto: in std_logic;<span> </span></div><div style="text-indent: 35.9pt" align="left">index2:in std_logic_vector(7 downto 0);<span> </span></div><div style="text-indent: 35.9pt" align="left">index0 : out std_logic_vector(7 downto 0));<span> </span></div><div style="text-indent: 10.5pt" align="left">end component;</div><div align="left">component tone</div><div style="text-indent: 10.5pt" align="left">Port ( index : in std_logic_vector(7 downto 0);<span> </span></div><div style="text-indent: 35.9pt" align="left">code : out std_logic_vector(6 downto 0);<span> </span></div><div style="text-indent: 35.9pt" align="left">high : out std_logic;<span> </span></div><div style="text-indent: 35.9pt" align="left">tone0 : out integer range 0 to 2047);</div><div style="text-indent: 10.5pt" align="left">end component;</div><div align="left">component speaker</div><div style="text-indent: 10.5pt" align="left">Port ( clk1 : in std_logic;</div><div style="text-indent: 27pt" align="left">tone1 : in integer range 0 to 2047;</div><div style="text-indent: 27pt" align="left">spks : out std_logic);</div><div style="text-indent: 10.5pt" align="left">end component;</div><div align="left">signal tone2: integer range 0 to 2047;</div><div align="left">signal indx:std_logic_vector(7 downto 0);</div><div align="left">begin</div><div style="text-indent: 8.9pt" align="left">u0:automusic port map(clk=>clk32MHZ,index2=>index1,index0=>indx,Auto=>handtoAuto);</div><div style="text-indent: 8.9pt" align="left">u1: tone port map(index=>indx,tone0=>tone2,code=>code1,high=>high1);</div><div style="text-indent: 8.9pt" align="left">u2: speaker port map(clk1=>clk32MHZ,tone1=>tone2,spks=>spkout);</div><div align="left">end Behavioral;</div><div>（2）仿真</div><div style="text-indent: 21pt">顶层文件仿真图如图8.18.2所示。</div><p> </p><p><img onload="ResizeImage(this,520)" src="http://www.dadwj.cn/upload/200805171509214462.JPG" alt="" title=""/></p><div align="center"><span style="font-size: 9pt">图8.18.2 顶层文件仿真图</span></div><div><span style="font-size: 12pt">2.</span><span style="font-size: 12pt">音阶发生器程序与仿真</span></div><div style="margin: 0cm 0cm 0pt 36pt; text-indent: -36pt"><span>（1）<span style="font: 7pt 'Times New Roman'"> </span></span>音阶发生器VHDL程序</div><div>--文件名：tone.vhd。</div><div>--功能：</div><div>library IEEE;</div><div>use IEEE.STD_LOGIC_1164.ALL;</div><div>use IEEE.STD_LOGIC_ARITH.ALL;</div><div>use IEEE.STD_LOGIC_UNSIGNED.ALL;</div><div>entity tone is</div><div style="text-indent: 10.5pt">Port ( index : in std_logic_vector(7 downto 0);<span> --</span>音符输入信号</div><div style="text-indent: 37.5pt">code : out std_logic_vector(6 downto 0);<span> --</span>音符显示信号</div><div style="text-indent: 37.5pt">high : out std_logic;<span> --</span>高低音显示信号</div><div style="text-indent: 37.5pt" align="left">tone0 : out integer range 0 to 2047);<span> --</span>音符的分频系数</div><div style="text-indent: 10.5pt">end tone;</div><div>architecture Behavioral of tone is</div><div>begin</div><div>search :process(index)<span> --</span>此进程完成音符到音符的分频系数译码，音符的显示，高低音阶</div><div>begin</div><div style="text-indent: 10.5pt">case index is</div><div style="text-indent: 27pt">when "00000001" => tone0<=773;code<="1001111";high<='1';</div><div style="text-indent: 27pt">when "00000010"=> tone0<=912;code<="0010010";high<='1';</div><div style="text-indent: 27pt">when "00000100" => tone0<=1036;code<="0000110";high<='1';</div><div style="text-indent: 27pt">when "00001000" => tone0<=1116;code<="1001100";high<='1';</div><div style="text-indent: 27pt">when "00010000" => tone0<=1197;code<="0100100";high<='1';</div><div style="text-indent: 27pt">when "00100000" => tone0<=1290;code<="0100000";high<='0';</div><div style="text-indent: 27pt">when "01000000" => tone0<=1372;code<="0001111";high<='0';</div><div style="text-indent: 27pt">when "10000000" => tone0<=1410;code<="0000000";high<='0';</div><div style="text-indent: 27pt">when<span> others => tone0<=2047;code<="0000001";high<='0';</span></div><div style="text-indent: 10.5pt">end case;</div><div>end process;</div><div>end Behavioral;</div><div>（2）音阶发生器程序仿真</div><p><span style="font-size: 10.5pt">音阶发生器程序仿真</span><span style="font-size: 10.5pt">图如图</span><span style="font-size: 10.5pt">8.18.3</span><span style="font-size: 10.5pt">所示。</span> </p><p><img onload="ResizeImage(this,520)" src="http://www.dadwj.cn/upload/200805171509381774.jpg" alt="" title=""/></p><div align="center"><span style="font-size: 9pt">图</span><span style="font-size: 9pt">8.18.3 </span><span style="font-size: 9pt">音阶发生器仿真图</span></div><div><span style="font-size: 12pt">3. </span><span style="font-size: 12pt">数控分频模块程序与仿真</span></div><div style="margin: 0cm 0cm 0pt 36pt; text-indent: -36pt"><span>（1）<span style="font: 7pt 'Times New Roman'"> </span></span>数控分频模块VHDL程序</div><div>--文件名：speaker.vhd。</div><div>--功 能：实现数控分频。</div><div>--最后修改日期：20004.3.19。</div><div>library IEEE;</div><div>use IEEE.STD_LOGIC_1164.ALL;</div><div>use IEEE.STD_LOGIC_ARITH.ALL;</div><div>use IEEE.STD_LOGIC_UNSIGNED.ALL;</div><div>entity speaker is</div><div style="text-indent: 10.5pt">Port ( clk1 : in std_logic;<span> --</span>系统时钟</div><div style="text-indent: 37.5pt">tone1 : in integer range 0 to 30624;<span> <span style="color: red"> </span>--</span>音符分频系数</div><div style="text-indent: 37.5pt">spks : out std_logic);<span> --</span>驱动扬声器的音频信号</div><div style="text-indent: 10.5pt">end speaker;</div><div>architecture Behavioral of speaker is</div><div>signal preclk,fullspks:std_logic;</div><div>begin</div><div>pulse1:process(clk1)<span> --</span>此进程对系统时钟进行4分频</div><div>variable count:integer range 0 to 8;</div><div>begin</div><div style="text-indent: 10.5pt">if clk1'event and clk1='1' then count:=count+1;</div><div style="text-indent: 21pt">if count=2 then preclk<='1'; </div><div style="text-indent: 21pt">elsif count=4 then preclk<='0';count:=0;</div><div style="text-indent: 21pt">end if;</div><div style="text-indent: 10.5pt">end if;</div><div>end process pulse1;</div><div>genspks:process(preclk,tone1)</div><div style="text-indent: 21pt">--此进程按照tone1输入的分频系数对8MHz的脉冲再次分频，得到所需要的音符频率</div><div>variable count11:integer range 0 to 30624;</div><div>begin</div><div style="text-indent: 10.5pt">if preclk'event and preclk='1' then</div><div style="text-indent: 21pt">if count11<tone1 then count11:=count11+1;fullspks<='1';</div><div style="text-indent: 21pt">else count11:=0;fullspks<='0';</div><div style="text-indent: 21pt">end if;</div><div style="text-indent: 10.5pt">end if;</div><div>end process;</div><div>delaysps:process(fullspks)<span> --</span>此进程对fullspks进行2分频</div><div>variable count2 :std_logic:='0';</div><div>begin</div><div style="text-indent: 10.5pt">if fullspks'event and fullspks='1' then count2:=not count2;</div><div style="text-indent: 21pt">if count2='1' then spks<='1';</div><div style="text-indent: 21pt">else spks<='0';</div><div style="text-indent: 21pt">end if;</div><div style="text-indent: 10.5pt">end if;</div><div>end process;</div><div>end Behavioral；</div><div>（2） 数控分频模块程序仿真</div><p><span style="font-size: 10.5pt">数控分频模块程序仿真图如图</span><span style="font-size: 10.5pt">8.18.4</span><span style="font-size: 10.5pt">所示。</span> </p><p><img onload="ResizeImage(this,520)" src="http://www.dadwj.cn/upload/200805171509590654.jpg" alt="" title=""/></p><div align="center"><span style="font-size: 9pt">图</span><span style="font-size: 9pt">8.18.4 </span><span style="font-size: 9pt">数控分频模块仿真图</span></div><div><span style="font-size: 12pt">4. </span><span style="font-size: 12pt">自动演奏模块程序与仿真</span></div><div style="margin: 0cm 0cm 0pt 36pt; text-indent: -36pt"><span>（1）<span style="font: 7pt 'Times New Roman'"> </span></span>自动演奏模块VHDL程序</div><div>--文件名：automusic.vhd</div><div>--功 能：实现自动演奏功能。</div><div>library IEEE;</div><div>use IEEE.STD_LOGIC_1164.ALL;</div><div>use IEEE.STD_LOGIC_ARITH.ALL;</div><div>use IEEE.STD_LOGIC_UNSIGNED.ALL;</div><div align="left">entity automusic is</div><div style="text-indent: 10.5pt" align="left">Port ( clk,Auto : in std_logic;<span> --</span>系统时钟；键盘输入/自动演奏</div><div style="text-indent: 35.9pt" align="left">index2 : in std_logic_vector(7 downto 0);<span> --</span>键盘输入信号</div><div style="text-indent: 35.9pt" align="left">index0 : out std_logic_vector(7 downto 0)); --音符信号输出</div><div style="text-indent: 10.5pt" align="left">end automusic;</div><div align="left">architecture Behavioral of automusic is</div><div style="text-indent: 10.5pt" align="left">signal count0:integer range 0 to 31;--change</div><div style="text-indent: 10.5pt" align="left">signal clk2:std_logic;</div><div align="left">begin</div><div>pulse0:process(clk,Auto)<span> --</span>此进程完成对系统时钟8M的分频，得到4Hz的信号clk2</div><div style="text-indent: 10.5pt">variable count:integer range 0 to 8000000;</div><div>begin</div><div style="text-indent: 10.5pt">if Auto='1' then count:=0;clk2<='0';</div><div style="text-indent: 10.5pt">elsif clk'event and clk='1' then count:=count+1;</div><div style="text-indent: 21pt">if count=4000000（4） then clk2<='1'; <span> </span></div><div style="text-indent: 21pt">elsif count=8000000 （8）then clk2<='0';count:=0;</div><div style="text-indent: 21pt">end if;</div><div style="text-indent: 10.5pt">end if;</div><div>end process;</div><div>music:process(clk2)<span> --</span>此进程完成自动演奏部分曲的地址累加</div><div>begin</div><div style="text-indent: 10.5pt">if clk2'event and clk2='1' then</div><div style="text-indent: 21pt">if count0=31 then count0<=0;</div><div style="text-indent: 21pt">else count0<=count0+1;</div><div style="text-indent: 21pt">end if;</div><div style="text-indent: 10.5pt">end if;</div><div>end process;</div><div>com1:process(count0,Auto,index2)<span> </span></div><div>begin</div><div style="text-indent: 10.5pt">if Auto='0' then</div><div style="text-indent: 21pt">case count0 is<span> --</span>此case语句：存储自动演奏部分的曲</div><div style="text-indent: 32.25pt">when 0 => index0<="00000100"; --3</div><div style="text-indent: 32.25pt">when 1 => index0<="00000100"; --3</div><div style="text-indent: 32.25pt">when 2 => index0<="00000100"; --3</div><div style="text-indent: 32.25pt">when 3 => index0<="00000100"; --3</div><div style="text-indent: 32.25pt">when 4 => index0<="00010000"; --5</div><div style="text-indent: 32.25pt">when 5 => index0<="00010000"; --5</div><div style="text-indent: 32.25pt">when 6 => index0<="00010000"; --5</div><div style="text-indent: 32.25pt">when 7 => index0<="00100000"; --6</div><div style="text-indent: 32.25pt">when 8 => index0<="10000000"; --8</div><div style="text-indent: 32.25pt">when 9 => index0<="10000000"; --8</div><div style="text-indent: 32.25pt">when 10 =>index0<="10000000"; --8</div><div style="text-indent: 32.25pt">when 11=> index0<="00000100"; --3</div><div style="text-indent: 32.25pt">when 12=> index0<="00000010"; --2</div><div style="text-indent: 32.25pt">when 13=> index0<="00000010"; --2</div><div style="text-indent: 32.25pt">when 14=> index0<="00000001"; --1</div><div style="text-indent: 32.25pt">when 15=> index0<="00000001"; --1</div><div style="text-indent: 32.25pt">when 16=> index0<="00010000"; --5</div><div style="text-indent: 32.25pt">when 17=> index0<="00010000"; --5</div><div style="text-indent: 32.25pt">when 18=> index0<="00001000"; --4</div><div style="text-indent: 32.25pt">when 19=> index0<="00001000"; --4</div><div style="text-indent: 32.25pt">when 20=> index0<="00001000"; --4</div><div style="text-indent: 32.25pt">when 21=> index0<="00000100"; --3</div><div style="text-indent: 32.25pt">when 22=> index0<="00000010"; --2</div><div style="text-indent: 32.25pt">when 23=> index0<="00000010"; --2</div><div style="text-indent: 32.25pt">when 24=> index0<="00010000"; --5</div><div style="text-indent: 32.25pt">when 25=> index0<="00010000"; --5</div><div style="text-indent: 32.25pt">when 26=> index0<="00001000"; --4</div><div style="text-indent: 32.25pt">when 27=> index0<="00001000"; --4</div><div style="text-indent: 32.25pt">when 28=> index0<="00000100"; --3</div><div style="text-indent: 32.25pt">when 29=> index0<="00000100"; --3</div><div style="text-indent: 32.25pt">when 30=> index0<="00000010"; --2</div><div style="text-indent: 32.25pt">when 31=> index0<="00000010"; --2</div><div style="text-indent: 32.25pt">when others => null;</div><div style="text-indent: 21pt">end case;</div><div style="text-indent: 10.5pt">else index0<=index2;<span> --</span>键盘输入音符信号输出</div><div style="text-indent: 10.5pt">end if;</div><div>end process;</div><div>end Behavioral;</div><div>（2）自动演奏模块程序仿真</div><p><span style="font-size: 10.5pt">自动演奏模块</span><span style="font-size: 10.5pt">仿真图如图</span><span style="font-size: 10.5pt">8.17.5</span><span style="font-size: 10.5pt">所示。</span> </p><p><img onload="ResizeImage(this,520)" src="http://www.dadwj.cn/upload/200805171510245620.jpg" alt="" title=""/></p><div align="center"><span style="font-size: 9pt">图</span><span style="font-size: 9pt">8.18.5 </span><span style="font-size: 9pt">自动演奏模块仿真图</span></div><div><span style="font-size: 9pt">（注：由于输入频率太高，实验条件所限，如按源程序仿真将看不到输出波形，因此将原脉冲的分频点</span><span style="font-size: 9pt">4000000</span><span style="font-size: 9pt">和</span><span style="font-size: 9pt">8000000</span><span style="font-size: 9pt">改为</span><span style="font-size: 9pt">4</span><span style="font-size: 9pt">和</span><span style="font-size: 9pt">8</span><span style="font-size: 9pt">，得到如图的仿真结果，在实际烧制芯片中不作此处理。）</span></div><p> </p>
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<input type="hidden" name="inpArticle" id="inpArticle" value="" />
<input type="hidden" name="inpLocation" id="inpLocation" value="" />
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