aa.tan.qmsg

对频率计闸门处复杂逻辑关系的处理

{ "Info" "ITDB_FULL_TPD_RESULT" "fenq count 7.963 ns Longest " "Info: Longest tpd from source pin \"fenq\" to destination pin \"count\" is 7.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns fenq 1 PIN PIN_R19 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_R19; Fanout = 1; PIN Node = 'fenq'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { fenq } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.155 ns) + CELL(0.280 ns) 4.669 ns count~36 2 COMB LC_X1_Y7_N5 1 " "Info: 2: + IC(3.155 ns) + CELL(0.280 ns) = 4.669 ns; Loc. = LC_X1_Y7_N5; Fanout = 1; COMB Node = 'count~36'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.435 ns" { fenq count~36 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(2.376 ns) 7.963 ns count 3 PIN PIN_R20 0 " "Info: 3: + IC(0.918 ns) + CELL(2.376 ns) = 7.963 ns; Loc. = PIN_R20; Fanout = 0; PIN Node = 'count'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.294 ns" { count~36 count } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.890 ns ( 48.85 % ) " "Info: Total cell delay = 3.890 ns ( 48.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.073 ns ( 51.15 % ) " "Info: Total interconnect delay = 4.073 ns ( 51.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.963 ns" { fenq count~36 count } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.963 ns" { fenq fenq~out0 count~36 count } { 0.000ns 0.000ns 3.155ns 0.918ns } { 0.000ns 1.234ns 0.280ns 2.376ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "flag1 gate cont 0.041 ns register " "Info: th for register \"flag1\" (data pin = \"gate\", clock pin = \"cont\") is 0.041 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cont destination 2.983 ns + Longest register " "Info: + Longest clock path from clock \"cont\" to destination register is 2.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns cont 1 CLK PIN_M20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'cont'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cont } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.613 ns) + CELL(0.542 ns) 2.983 ns flag1 2 REG LC_X1_Y7_N6 3 " "Info: 2: + IC(1.613 ns) + CELL(0.542 ns) = 2.983 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.155 ns" { cont flag1 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.93 % ) " "Info: Total cell delay = 1.370 ns ( 45.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.613 ns ( 54.07 % ) " "Info: Total interconnect delay = 1.613 ns ( 54.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 flag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.042 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.042 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns gate 1 CLK PIN_M21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 5; CLK Node = 'gate'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.998 ns) + CELL(0.319 ns) 3.042 ns flag1 2 REG LC_X1_Y7_N6 3 " "Info: 2: + IC(1.998 ns) + CELL(0.319 ns) = 3.042 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.317 ns" { gate flag1 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.044 ns ( 34.32 % ) " "Info: Total cell delay = 1.044 ns ( 34.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.998 ns ( 65.68 % ) " "Info: Total interconnect delay = 1.998 ns ( 65.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.042 ns" { gate flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.042 ns" { gate gate~out0 flag1 } { 0.000ns 0.000ns 1.998ns } { 0.000ns 0.725ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 flag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.042 ns" { gate flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.042 ns" { gate gate~out0 flag1 } { 0.000ns 0.000ns 1.998ns } { 0.000ns 0.725ns 0.319ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 19 08:43:47 2008 " "Info: Processing ended: Wed Mar 19 08:43:47 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}