aa.vhd

来自「对频率计闸门处复杂逻辑关系的处理」· VHDL 代码 · 共 56 行

library ieee;
use ieee.std_logic_1164.all;
entity aa is
	port(cont,gate,fenq,DATERD:in std_logic;
	     count,kk:out std_logic);
end entity aa;

architecture bb of aa is
	signal flag1,flag2,flag3,sedflag1:std_logic;
begin
	P1:process (cont,flag2,flag3)
	
	   begin
	   		if flag2='1' then 
				flag1<='0';
			elsif flag3='1' then
				sedflag1<='0';
			elsif rising_edge(cont) then
				if gate='0' then
					flag1<='1';
				
				else
					sedflag1<='1';
				end if;
			end if;
	   end process P1;
	P2:count<=fenq and gate and (flag1 or flag3);
	
	P3:process (gate,DATERD)
	   begin
			if DATERD='0' then
				flag2<='0';kk<='0';
			elsif falling_edge(gate)then
				if flag1='1'  or flag3='1' then
					flag2<='1';
					kk<='1';
				elsif flag3='1' then 
					kk<='1';
				end if;
			end if;
	   end process P3;
	P4:process(gate,flag2,sedflag1)
	   begin
			if flag2='1' then
			   flag3<='0';
			elsif rising_edge(gate) then
				if sedflag1='1' then
					flag3<='1';
				end if;
			end if;
		end process;
				   			
end architecture bb ;