📄 aa.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "gate register register flag3 kk~reg0 422.12 MHz Internal " "Info: Clock \"gate\" Internal fmax is restricted to 422.12 MHz between source register \"flag3\" and destination register \"kk~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.793 ns + Longest register register " "Info: + Longest register to register delay is 0.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns flag3 1 REG LC_X2_Y7_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y7_N5; Fanout = 5; REG Node = 'flag3'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { flag3 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.570 ns) + CELL(0.223 ns) 0.793 ns kk~reg0 2 REG LC_X1_Y7_N8 6 " "Info: 2: + IC(0.570 ns) + CELL(0.223 ns) = 0.793 ns; Loc. = LC_X1_Y7_N8; Fanout = 6; REG Node = 'kk~reg0'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.793 ns" { flag3 kk~reg0 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 31 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.223 ns ( 28.12 % ) " "Info: Total cell delay = 0.223 ns ( 28.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.570 ns ( 71.88 % ) " "Info: Total interconnect delay = 0.570 ns ( 71.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.793 ns" { flag3 kk~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.793 ns" { flag3 kk~reg0 } { 0.000ns 0.570ns } { 0.000ns 0.223ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "gate destination 2.907 ns + Shortest register " "Info: + Shortest clock path from clock \"gate\" to destination register is 2.907 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns gate 1 CLK PIN_M21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 5; CLK Node = 'gate'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.640 ns) + CELL(0.542 ns) 2.907 ns kk~reg0 2 REG LC_X1_Y7_N8 6 " "Info: 2: + IC(1.640 ns) + CELL(0.542 ns) = 2.907 ns; Loc. = LC_X1_Y7_N8; Fanout = 6; REG Node = 'kk~reg0'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.182 ns" { gate kk~reg0 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 31 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.58 % ) " "Info: Total cell delay = 1.267 ns ( 43.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.640 ns ( 56.42 % ) " "Info: Total interconnect delay = 1.640 ns ( 56.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.907 ns" { gate kk~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.907 ns" { gate gate~out0 kk~reg0 } { 0.000ns 0.000ns 1.640ns } { 0.000ns 0.725ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "gate source 2.907 ns - Longest register " "Info: - Longest clock path from clock \"gate\" to source register is 2.907 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns gate 1 CLK PIN_M21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 5; CLK Node = 'gate'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.640 ns) + CELL(0.542 ns) 2.907 ns flag3 2 REG LC_X2_Y7_N5 5 " "Info: 2: + IC(1.640 ns) + CELL(0.542 ns) = 2.907 ns; Loc. = LC_X2_Y7_N5; Fanout = 5; REG Node = 'flag3'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.182 ns" { gate flag3 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.58 % ) " "Info: Total cell delay = 1.267 ns ( 43.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.640 ns ( 56.42 % ) " "Info: Total interconnect delay = 1.640 ns ( 56.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.907 ns" { gate flag3 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.907 ns" { gate gate~out0 flag3 } { 0.000ns 0.000ns 1.640ns } { 0.000ns 0.725ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.907 ns" { gate kk~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.907 ns" { gate gate~out0 kk~reg0 } { 0.000ns 0.000ns 1.640ns } { 0.000ns 0.725ns 0.542ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.907 ns" { gate flag3 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.907 ns" { gate gate~out0 flag3 } { 0.000ns 0.000ns 1.640ns } { 0.000ns 0.725ns 0.542ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 31 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 31 0 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.793 ns" { flag3 kk~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.793 ns" { flag3 kk~reg0 } { 0.000ns 0.570ns } { 0.000ns 0.223ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.907 ns" { gate kk~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.907 ns" { gate gate~out0 kk~reg0 } { 0.000ns 0.000ns 1.640ns } { 0.000ns 0.725ns 0.542ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.907 ns" { gate flag3 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.907 ns" { gate gate~out0 flag3 } { 0.000ns 0.000ns 1.640ns } { 0.000ns 0.725ns 0.542ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { kk~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { kk~reg0 } { } { } "" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 31 0 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "cont register register flag1 flag1 422.12 MHz Internal " "Info: Clock \"cont\" Internal fmax is restricted to 422.12 MHz between source register \"flag1\" and destination register \"flag1\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.614 ns + Longest register register " "Info: + Longest register to register delay is 0.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns flag1 1 REG LC_X1_Y7_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { flag1 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.223 ns) 0.614 ns flag1 2 REG LC_X1_Y7_N6 3 " "Info: 2: + IC(0.391 ns) + CELL(0.223 ns) = 0.614 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.614 ns" { flag1 flag1 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.223 ns ( 36.32 % ) " "Info: Total cell delay = 0.223 ns ( 36.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.391 ns ( 63.68 % ) " "Info: Total interconnect delay = 0.391 ns ( 63.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.614 ns" { flag1 flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.614 ns" { flag1 flag1 } { 0.000ns 0.391ns } { 0.000ns 0.223ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cont destination 2.983 ns + Shortest register " "Info: + Shortest clock path from clock \"cont\" to destination register is 2.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns cont 1 CLK PIN_M20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'cont'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cont } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.613 ns) + CELL(0.542 ns) 2.983 ns flag1 2 REG LC_X1_Y7_N6 3 " "Info: 2: + IC(1.613 ns) + CELL(0.542 ns) = 2.983 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.155 ns" { cont flag1 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.93 % ) " "Info: Total cell delay = 1.370 ns ( 45.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.613 ns ( 54.07 % ) " "Info: Total interconnect delay = 1.613 ns ( 54.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 flag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cont source 2.983 ns - Longest register " "Info: - Longest clock path from clock \"cont\" to source register is 2.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns cont 1 CLK PIN_M20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'cont'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cont } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.613 ns) + CELL(0.542 ns) 2.983 ns flag1 2 REG LC_X1_Y7_N6 3 " "Info: 2: + IC(1.613 ns) + CELL(0.542 ns) = 2.983 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.155 ns" { cont flag1 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.93 % ) " "Info: Total cell delay = 1.370 ns ( 45.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.613 ns ( 54.07 % ) " "Info: Total interconnect delay = 1.613 ns ( 54.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 flag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 flag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 flag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.614 ns" { flag1 flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.614 ns" { flag1 flag1 } { 0.000ns 0.391ns } { 0.000ns 0.223ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 flag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 flag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { flag1 } { } { } "" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sedflag1 gate cont 0.287 ns register " "Info: tsu for register \"sedflag1\" (data pin = \"gate\", clock pin = \"cont\") is 0.287 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.260 ns + Longest pin register " "Info: + Longest pin to register delay is 3.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns gate 1 CLK PIN_M21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 5; CLK Node = 'gate'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { gate } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.996 ns) + CELL(0.539 ns) 3.260 ns sedflag1 2 REG LC_X2_Y7_N9 2 " "Info: 2: + IC(1.996 ns) + CELL(0.539 ns) = 3.260 ns; Loc. = LC_X2_Y7_N9; Fanout = 2; REG Node = 'sedflag1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { gate sedflag1 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.264 ns ( 38.77 % ) " "Info: Total cell delay = 1.264 ns ( 38.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.996 ns ( 61.23 % ) " "Info: Total interconnect delay = 1.996 ns ( 61.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.260 ns" { gate sedflag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.260 ns" { gate gate~out0 sedflag1 } { 0.000ns 0.000ns 1.996ns } { 0.000ns 0.725ns 0.539ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cont destination 2.983 ns - Shortest register " "Info: - Shortest clock path from clock \"cont\" to destination register is 2.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns cont 1 CLK PIN_M20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'cont'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cont } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.613 ns) + CELL(0.542 ns) 2.983 ns sedflag1 2 REG LC_X2_Y7_N9 2 " "Info: 2: + IC(1.613 ns) + CELL(0.542 ns) = 2.983 ns; Loc. = LC_X2_Y7_N9; Fanout = 2; REG Node = 'sedflag1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.155 ns" { cont sedflag1 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.93 % ) " "Info: Total cell delay = 1.370 ns ( 45.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.613 ns ( 54.07 % ) " "Info: Total interconnect delay = 1.613 ns ( 54.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont sedflag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 sedflag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.260 ns" { gate sedflag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.260 ns" { gate gate~out0 sedflag1 } { 0.000ns 0.000ns 1.996ns } { 0.000ns 0.725ns 0.539ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont sedflag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 sedflag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "cont count flag1 7.146 ns register " "Info: tco from clock \"cont\" to destination pin \"count\" through register \"flag1\" is 7.146 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cont source 2.983 ns + Longest register " "Info: + Longest clock path from clock \"cont\" to source register is 2.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns cont 1 CLK PIN_M20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'cont'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cont } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.613 ns) + CELL(0.542 ns) 2.983 ns flag1 2 REG LC_X1_Y7_N6 3 " "Info: 2: + IC(1.613 ns) + CELL(0.542 ns) = 2.983 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.155 ns" { cont flag1 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.93 % ) " "Info: Total cell delay = 1.370 ns ( 45.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.613 ns ( 54.07 % ) " "Info: Total interconnect delay = 1.613 ns ( 54.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 flag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.007 ns + Longest register pin " "Info: + Longest register to pin delay is 4.007 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns flag1 1 REG LC_X1_Y7_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { flag1 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.530 ns) + CELL(0.183 ns) 0.713 ns count~36 2 COMB LC_X1_Y7_N5 1 " "Info: 2: + IC(0.530 ns) + CELL(0.183 ns) = 0.713 ns; Loc. = LC_X1_Y7_N5; Fanout = 1; COMB Node = 'count~36'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.713 ns" { flag1 count~36 } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(2.376 ns) 4.007 ns count 3 PIN PIN_R20 0 " "Info: 3: + IC(0.918 ns) + CELL(2.376 ns) = 4.007 ns; Loc. = PIN_R20; Fanout = 0; PIN Node = 'count'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.294 ns" { count~36 count } "NODE_NAME" } } { "aa.vhd" "" { Text "F:/verilog/M-add flag3 yzy/aa.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.559 ns ( 63.86 % ) " "Info: Total cell delay = 2.559 ns ( 63.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.448 ns ( 36.14 % ) " "Info: Total interconnect delay = 1.448 ns ( 36.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.007 ns" { flag1 count~36 count } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.007 ns" { flag1 count~36 count } { 0.000ns 0.530ns 0.918ns } { 0.000ns 0.183ns 2.376ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.983 ns" { cont flag1 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.983 ns" { cont cont~out0 flag1 } { 0.000ns 0.000ns 1.613ns } { 0.000ns 0.828ns 0.542ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.007 ns" { flag1 count~36 count } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.007 ns" { flag1 count~36 count } { 0.000ns 0.530ns 0.918ns } { 0.000ns 0.183ns 2.376ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
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