aa.hier_info

对频率计闸门处复杂逻辑关系的处理

|aa
cont => sedflag1.CLK
cont => flag1.CLK
gate => count~0.IN0
gate => flag3.CLK
gate => flag1~0.OUTPUTSELECT
gate => kk~reg0.CLK
gate => flag2.CLK
gate => sedflag1~0.OUTPUTSELECT
fenq => count~0.IN1
DATERD => kk~reg0.ACLR
DATERD => flag2.ACLR
count <= count~2.DB_MAX_OUTPUT_PORT_TYPE
kk <= kk~reg0.DB_MAX_OUTPUT_PORT_TYPE