aa.tan.rpt

对频率计闸门处复杂逻辑关系的处理

; N/A   ; None         ; 7.004 ns   ; flag3   ; count ; gate       ;
; N/A   ; None         ; 6.678 ns   ; kk~reg0 ; kk    ; gate       ;
+-------+--------------+------------+---------+-------+------------+


+------------------------------------------------------------+
; tpd                                                        ;
+-------+-------------------+-----------------+------+-------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To    ;
+-------+-------------------+-----------------+------+-------+
; N/A   ; None              ; 7.963 ns        ; fenq ; count ;
; N/A   ; None              ; 6.384 ns        ; gate ; count ;
+-------+-------------------+-----------------+------+-------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; 0.041 ns  ; gate ; flag1    ; cont     ;
; N/A           ; None        ; -0.177 ns ; gate ; sedflag1 ; cont     ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Mar 19 08:43:46 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off aa -c aa --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "gate" is an undefined clock
    Info: Assuming node "cont" is an undefined clock
Info: Clock "gate" Internal fmax is restricted to 422.12 MHz between source register "flag3" and destination register "kk~reg0"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.793 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y7_N5; Fanout = 5; REG Node = 'flag3'
            Info: 2: + IC(0.570 ns) + CELL(0.223 ns) = 0.793 ns; Loc. = LC_X1_Y7_N8; Fanout = 6; REG Node = 'kk~reg0'
            Info: Total cell delay = 0.223 ns ( 28.12 % )
            Info: Total interconnect delay = 0.570 ns ( 71.88 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "gate" to destination register is 2.907 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 5; CLK Node = 'gate'
                Info: 2: + IC(1.640 ns) + CELL(0.542 ns) = 2.907 ns; Loc. = LC_X1_Y7_N8; Fanout = 6; REG Node = 'kk~reg0'
                Info: Total cell delay = 1.267 ns ( 43.58 % )
                Info: Total interconnect delay = 1.640 ns ( 56.42 % )
            Info: - Longest clock path from clock "gate" to source register is 2.907 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 5; CLK Node = 'gate'
                Info: 2: + IC(1.640 ns) + CELL(0.542 ns) = 2.907 ns; Loc. = LC_X2_Y7_N5; Fanout = 5; REG Node = 'flag3'
                Info: Total cell delay = 1.267 ns ( 43.58 % )
                Info: Total interconnect delay = 1.640 ns ( 56.42 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
        Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: Clock "cont" Internal fmax is restricted to 422.12 MHz between source register "flag1" and destination register "flag1"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.614 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'
            Info: 2: + IC(0.391 ns) + CELL(0.223 ns) = 0.614 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'
            Info: Total cell delay = 0.223 ns ( 36.32 % )
            Info: Total interconnect delay = 0.391 ns ( 63.68 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "cont" to destination register is 2.983 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'cont'
                Info: 2: + IC(1.613 ns) + CELL(0.542 ns) = 2.983 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'
                Info: Total cell delay = 1.370 ns ( 45.93 % )
                Info: Total interconnect delay = 1.613 ns ( 54.07 % )
            Info: - Longest clock path from clock "cont" to source register is 2.983 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'cont'
                Info: 2: + IC(1.613 ns) + CELL(0.542 ns) = 2.983 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'
                Info: Total cell delay = 1.370 ns ( 45.93 % )
                Info: Total interconnect delay = 1.613 ns ( 54.07 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "sedflag1" (data pin = "gate", clock pin = "cont") is 0.287 ns
    Info: + Longest pin to register delay is 3.260 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 5; CLK Node = 'gate'
        Info: 2: + IC(1.996 ns) + CELL(0.539 ns) = 3.260 ns; Loc. = LC_X2_Y7_N9; Fanout = 2; REG Node = 'sedflag1'
        Info: Total cell delay = 1.264 ns ( 38.77 % )
        Info: Total interconnect delay = 1.996 ns ( 61.23 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "cont" to destination register is 2.983 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'cont'
        Info: 2: + IC(1.613 ns) + CELL(0.542 ns) = 2.983 ns; Loc. = LC_X2_Y7_N9; Fanout = 2; REG Node = 'sedflag1'
        Info: Total cell delay = 1.370 ns ( 45.93 % )
        Info: Total interconnect delay = 1.613 ns ( 54.07 % )
Info: tco from clock "cont" to destination pin "count" through register "flag1" is 7.146 ns
    Info: + Longest clock path from clock "cont" to source register is 2.983 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'cont'
        Info: 2: + IC(1.613 ns) + CELL(0.542 ns) = 2.983 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'
        Info: Total cell delay = 1.370 ns ( 45.93 % )
        Info: Total interconnect delay = 1.613 ns ( 54.07 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.007 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'
        Info: 2: + IC(0.530 ns) + CELL(0.183 ns) = 0.713 ns; Loc. = LC_X1_Y7_N5; Fanout = 1; COMB Node = 'count~36'
        Info: 3: + IC(0.918 ns) + CELL(2.376 ns) = 4.007 ns; Loc. = PIN_R20; Fanout = 0; PIN Node = 'count'
        Info: Total cell delay = 2.559 ns ( 63.86 % )
        Info: Total interconnect delay = 1.448 ns ( 36.14 % )
Info: Longest tpd from source pin "fenq" to destination pin "count" is 7.963 ns
    Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_R19; Fanout = 1; PIN Node = 'fenq'
    Info: 2: + IC(3.155 ns) + CELL(0.280 ns) = 4.669 ns; Loc. = LC_X1_Y7_N5; Fanout = 1; COMB Node = 'count~36'
    Info: 3: + IC(0.918 ns) + CELL(2.376 ns) = 7.963 ns; Loc. = PIN_R20; Fanout = 0; PIN Node = 'count'
    Info: Total cell delay = 3.890 ns ( 48.85 % )
    Info: Total interconnect delay = 4.073 ns ( 51.15 % )
Info: th for register "flag1" (data pin = "gate", clock pin = "cont") is 0.041 ns
    Info: + Longest clock path from clock "cont" to destination register is 2.983 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 2; CLK Node = 'cont'
        Info: 2: + IC(1.613 ns) + CELL(0.542 ns) = 2.983 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'
        Info: Total cell delay = 1.370 ns ( 45.93 % )
        Info: Total interconnect delay = 1.613 ns ( 54.07 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 3.042 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 5; CLK Node = 'gate'
        Info: 2: + IC(1.998 ns) + CELL(0.319 ns) = 3.042 ns; Loc. = LC_X1_Y7_N6; Fanout = 3; REG Node = 'flag1'
        Info: Total cell delay = 1.044 ns ( 34.32 % )
        Info: Total interconnect delay = 1.998 ns ( 65.68 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Wed Mar 19 08:43:47 2008
    Info: Elapsed time: 00:00:01